Index: Build
===================================================================
RCS file: Build
diff -N Build
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ Build	23 Feb 2005 17:03:38 -0000	1.3
@@ -0,0 +1,9 @@
+#!/bin/sh
+
+source ../../Config.sh
+
+pp_build_local () {
+    make PEPPERCON_config && make install
+}
+
+pp_do "$@"
Index: Makefile
===================================================================
RCS file: /srv/CVS/pplinux/u-boot/Makefile,v
retrieving revision 1.1.333.1
retrieving revision 1.3
diff -u -r1.1.333.1 -r1.3
--- Makefile	3 Feb 2005 09:43:11 -0000	1.1.333.1
+++ Makefile	23 Feb 2005 17:03:38 -0000	1.3
@@ -21,6 +21,9 @@
 # MA 02111-1307 USA
 #
 
+USE_REAL_CROSS = 1
+include ../../Config.mk
+
 HOSTARCH := $(shell uname -m | \
 	sed -e s/i.86/i386/ \
 	    -e s/sun4u/sparc64/ \
@@ -75,25 +78,26 @@
 endif
 endif
 
+CROSS_COMPILE = $(CROSS)
+
 export	CROSS_COMPILE
 
 # The "tools" are needed early, so put this first
 SUBDIRS	= tools \
-	  examples \
 	  lib_generic \
 	  lib_$(ARCH) \
 	  cpu/$(CPU) \
 	  board/$(BOARDDIR) \
 	  common \
-	  disk \
-	  fs \
 	  net \
 	  rtc \
-	  dtt \
 	  drivers \
-	  drivers/sk98lin \
 	  post \
 	  post/cpu
+#	 fs \
+#	 disk \
+#	 dtt \
+#	 drivers/sk98lin
 
 #########################################################################
 # U-Boot objects....order is important (i.e. start must be first)
@@ -113,18 +117,18 @@
 LIBS  =	board/$(BOARDDIR)/lib$(BOARD).a
 LIBS += cpu/$(CPU)/lib$(CPU).a
 LIBS += lib_$(ARCH)/lib$(ARCH).a
-LIBS += fs/jffs2/libjffs2.a fs/fdos/libfdos.a fs/fat/libfat.a
+#LIBS += fs/jffs2/libjffs2.a fs/fdos/libfdos.a fs/fat/libfat.a
 LIBS += net/libnet.a
-LIBS += disk/libdisk.a
+#LIBS += disk/libdisk.a
 LIBS += rtc/librtc.a
-LIBS += dtt/libdtt.a
+#LIBS += dtt/libdtt.a
 LIBS += drivers/libdrivers.a
-LIBS += drivers/sk98lin/libsk98lin.a
+#LIBS += drivers/sk98lin/libsk98lin.a
 LIBS += post/libpost.a post/cpu/libcpu.a
 LIBS += common/libcommon.a
 LIBS += lib_generic/libgeneric.a
 # Add GCC lib
-PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc
+#PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc
 
 #########################################################################
 #########################################################################
@@ -133,6 +137,39 @@
 
 all:		$(ALL)
 
+install: all
+ifeq ($(PP_PRODUCTION),1)
+
+# PP_PRODUCTION
+
+  ifeq ($(PP_BOARD),lara)
+    ifeq ($(PP_SUBBOARD),none)
+	cp -f u-boot.bin /tftpboot/u-boot.lara.prod
+    else
+	cp -f u-boot.bin /tftpboot/u-boot.lara.$(PP_SUBBOARD).prod
+    endif
+  else
+    ifeq ($(PP_BOARD),eric)
+	cp -f u-boot.bin /tftpboot/u-boot.eric.prod
+    endif
+  endif
+
+else
+
+# ! PP_PRODUCTION
+	cp -f u-boot.bin /tftpboot/u-boot.$(PP_BOARD).$(PP_SUBBOARD).$(USER)
+
+  ifeq ($(PP_BUILD_TYPE),final)
+	cp -f u-boot.bin $(FW_TOPDIR)/mkfirmware/
+  endif
+
+endif
+
+pp_have_405ep:
+		@$(CPP) -dM $(CPPFLAGS) include/config.h | \
+		  grep '^#.*define.*CONFIG_405EP.*1$$' > /dev/null && \
+		  echo 1 || echo 0
+
 u-boot.srec:	u-boot
 		$(OBJCOPY) ${OBJCFLAGS} -O srec $< $@
 
@@ -179,7 +216,7 @@
 
 #########################################################################
 else
-all install u-boot u-boot.srec depend dep:
+all install u-boot u-boot.srec depend dep pp_have_405ep:
 	@echo "System not configured - see README" >&2
 	@ exit 1
 endif
@@ -530,8 +567,8 @@
 EBONY_config:unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx ebony
 
-ERIC_config:unconfig
-	@./mkconfig $(@:_config=) ppc ppc4xx eric
+PEPPERCON_config:unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx peppercon
 
 EXBITGEN_config:unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx exbitgen
Index: config.mk
===================================================================
RCS file: /srv/CVS/pplinux/u-boot/config.mk,v
retrieving revision 1.1.333.1
retrieving revision 1.3
diff -u -r1.1.333.1 -r1.3
--- config.mk	3 Feb 2005 09:43:11 -0000	1.1.333.1
+++ config.mk	23 Feb 2005 17:03:38 -0000	1.3
@@ -23,6 +23,9 @@
 
 #########################################################################
 
+USE_REAL_CROSS = 1
+include $(TOPDIR)/../../Config.mk
+
 # clean the slate ...
 PLATFORM_RELFLAGS =
 PLATFORM_CPPFLAGS =
@@ -99,7 +102,7 @@
 RANLIB	= $(CROSS_COMPILE)RANLIB
 
 RELFLAGS= $(PLATFORM_RELFLAGS)
-DBGFLAGS= -g #-DDEBUG
+DBGFLAGS= #-g -DDEBUG
 OPTFLAGS= -Os #-fomit-frame-pointer
 ifndef LDSCRIPT
 #LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds.debug
@@ -111,9 +114,9 @@
 
 CPPFLAGS := $(DBGFLAGS) $(OPTFLAGS) $(RELFLAGS)		\
 	-D__KERNEL__ -DTEXT_BASE=$(TEXT_BASE)		\
-	-I$(TOPDIR)/include				\
+	-I$(TOPDIR)/include -I$(TOPDIR)/board/$(BOARD)	\
 	-fno-builtin -ffreestanding -nostdinc -isystem	\
-	$(gccincdir) -pipe $(PLATFORM_CPPFLAGS)
+	$(gccincdir) -pipe $(PLATFORM_CPPFLAGS) $(FW_CPPFLAGS)
 
 ifdef BUILD_TAG
 CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes \
@@ -121,11 +124,14 @@
 else
 CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes
 endif
+# We put ech function and variable in its own section. The linker throws
+# all unused stuff away later if called with --gc-sections
+CFLAGS += -fdata-sections -ffunction-sections -Werror
 
 AFLAGS_DEBUG := -Wa,-gstabs
 AFLAGS := $(AFLAGS_DEBUG) -D__ASSEMBLY__ $(CPPFLAGS)
 
-LDFLAGS += -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+LDFLAGS += -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) --cref --gc-sections
 
 # Location of a usable BFD library, where we define "usable" as
 # "built for ${HOST}, supports ${TARGET}".  Sensible values are
Index: board/peppercon/.dontdelete
===================================================================
RCS file: board/peppercon/.dontdelete
diff -N board/peppercon/.dontdelete
Index: board/peppercon/Makefile
===================================================================
RCS file: board/peppercon/Makefile
diff -N board/peppercon/Makefile
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ board/peppercon/Makefile	3 Feb 2005 10:35:41 -0000	1.1
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o strataflash.o
+SOBJS	= init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
Index: board/peppercon/config.mk
===================================================================
RCS file: board/peppercon/config.mk
diff -N board/peppercon/config.mk
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ board/peppercon/config.mk	3 Feb 2005 10:35:41 -0000	1.1
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd ADCIOP boards
+#
+
+#TEXT_BASE = 0xFFF80000
+#TEXT_BASE = 0xFFFC0000
+TEXT_BASE = 0xFFFE0000
+OBJCFLAGS = --set-section-flags=.ppcenv=contents,alloc,load,data
Index: board/peppercon/hw_0E.h
===================================================================
RCS file: board/peppercon/hw_0E.h
diff -N board/peppercon/hw_0E.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ board/peppercon/hw_0E.h	2 May 2005 08:59:25 -0000	1.4
@@ -0,0 +1,598 @@
+/******************************************************************************
+ *
+ * Hardware configuration of KIM 1.1 / MB "B52"
+ *
+ * Hardware-ID: 0x0E
+ *
+ */  
+
+#ifndef _HW_0E_H
+#define _HW_0E_H
+
+/* ----------------------------------------------------------------------------
+ * Miscellaneous Hardware Configuration
+ */
+
+#define PP_HWID_0E_CPU_TYPE		PP_CPU_405EP	/* The CPU type */
+#define PP_HWID_0E_FLASH_SIZE		(8*1024*1024)	/* Flash size in bytes */
+#define PP_HWID_0E_SDRAM_ROWS		4096		/* SDRAM row count */
+#define PP_HWID_0E_SDRAM_B0CR		0x00062001	/* 32MB @ 0x0 12x9x4 */
+#define PP_HWID_0E_SDRAM_RTR		0x0618		/* 100 MHz; 64ms; 4k refresh */
+#define PP_HWID_0E_SDRAM_TR		0x0086400D	/* 100 MHz; CASL=2, PTA=2, CTP=3, LDF=2, RFTA=7, RCD=2 */
+#define PP_HWID_0E_SYS_CLK_FREQ		33333333	/* external frequency to PLL */
+#define PP_HWID_0E_PHY_LED_CFG_VALUE	0x0472		/* LXT972A; register 0x14 */
+#define PP_HWID_0E_BIGPHYSAREA_PAGES	980		/* # of reserved pages for linux */
+#define PP_HWID_0E_CONSOLE              PP_SERIAL_0
+
+#define PP_HWID_0E_DESCRIPTION		"KIM 1.2 / FPGA C4"
+
+/* ----------------------------------------------------------------------------
+ * The PLL configuration (see PPC405EP manual section 7.2, 7.5.3 and 7.5.4)
+ */
+
+#define PP_HWID_0E_DYNAMIC_PLL	   0
+
+/* ------------- 33 MHz SysClk Settings --------------- */
+/* Slow (66 MHz CPU-Clk, 33MHz bus) */
+#define PP_HWID_0E_PLLMR0_SLOW (PLL_CPUDIV_2		\
+				   | PLL_PLBDIV_1	\
+				   | PLL_OPBDIV_2	\
+				   | PLL_EXTBUSDIV_2	\
+				   | PLL_MALDIV_1	\
+				   | PLL_PCIDIV_4)
+
+#define PP_HWID_0E_PLLMR1_SLOW (PLL_FBKDIV_6		\
+				   | PLL_FWDDIVA_4	\
+				   | PLL_FWDDIVB_4	\
+				   | PLL_TUNE_15_M_40	\
+				   | PLL_TUNE_VCO_LOW)
+
+/* Fast (200 MHz CPU-Clk, 50 MHz bus) */
+#if defined(PRODUCT_FLASHX4)
+# define PP_HWID_0E_PLLMR0_FAST (PLL_CPUDIV_1		\
+				   | PLL_PLBDIV_2	\
+				   | PLL_OPBDIV_2	\
+				   | PLL_EXTBUSDIV_4	\
+				   | PLL_MALDIV_1	\
+				   | PLL_PCIDIV_3)
+#else /* !PRODUCT_FLASHX4 */
+# define PP_HWID_0E_PLLMR0_FAST (PLL_CPUDIV_1		\
+				   | PLL_PLBDIV_2	\
+				   | PLL_OPBDIV_2	\
+				   | PLL_EXTBUSDIV_2	\
+				   | PLL_MALDIV_1	\
+				   | PLL_PCIDIV_3)
+#endif /* !PRODUCT_FLASHX4 */
+
+
+#define PP_HWID_0E_PLLMR1_FAST (PLL_FBKDIV_6		\
+				   | PLL_FWDDIVA_4	\
+				   | PLL_FWDDIVB_4	\
+				   | PLL_TUNE_15_M_40	\
+				   | PLL_TUNE_VCO_LOW)
+					
+#define PP_HWID_0E_PLLMR0_DEFAULT	PP_HWID_0E_PLLMR0_FAST
+#define PP_HWID_0E_PLLMR1_DEFAULT	PP_HWID_0E_PLLMR1_FAST
+
+/* ----------------------------------------------------------------------------
+ * GPIO configuration
+ */
+
+/* GPIO 0: Unused */
+#define PP_HWID_0E_GPIO_00_IS_OUTPUT		0
+#define PP_HWID_0E_GPIO_00_IS_OPEN_DRAIN	0
+#define PP_HWID_0E_GPIO_00_OUTPUT_VALUE		0
+#define PP_HWID_0E_GPIO_00_IS_GPIO		0
+
+/* GPIO 1: ATMEL_MISO */
+#define PP_HWID_0E_GPIO_01_IS_OUTPUT		0
+#define PP_HWID_0E_GPIO_01_IS_OPEN_DRAIN	0
+#define PP_HWID_0E_GPIO_01_OUTPUT_VALUE		0
+#define PP_HWID_0E_GPIO_01_IS_GPIO		1
+
+/* GPIO 2: ATMEL MOSI / FPGA_TDI */
+#define PP_HWID_0E_GPIO_02_IS_OUTPUT		1
+#define PP_HWID_0E_GPIO_02_IS_OPEN_DRAIN	0
+#define PP_HWID_0E_GPIO_02_OUTPUT_VALUE		0
+#define PP_HWID_0E_GPIO_02_IS_GPIO		1
+
+/* GPIO 3: ATMEL_RST */
+#define PP_HWID_0E_GPIO_03_IS_OUTPUT		1
+#define PP_HWID_0E_GPIO_03_IS_OPEN_DRAIN	0
+#define PP_HWID_0E_GPIO_03_OUTPUT_VALUE		0
+#define PP_HWID_0E_GPIO_03_IS_GPIO		1
+
+/* GPIO 4: ATMEL_SCK / FPGA_TCK */
+#define PP_HWID_0E_GPIO_04_IS_OUTPUT		1
+#define PP_HWID_0E_GPIO_04_IS_OPEN_DRAIN	0
+#define PP_HWID_0E_GPIO_04_OUTPUT_VALUE		0
+#define PP_HWID_0E_GPIO_04_IS_GPIO		1
+
+#if PP_FEAT_AD_ATMEL
+/* GPIO 5: A/D Atmel reset pin */
+#define PP_HWID_0E_GPIO_05_IS_OUTPUT		1
+#define PP_HWID_0E_GPIO_05_IS_OPEN_DRAIN	0
+#define PP_HWID_0E_GPIO_05_OUTPUT_VALUE		0
+#define PP_HWID_0E_GPIO_05_IS_GPIO		1
+#else
+/* GPIO 5: Default Jumper */
+#define PP_HWID_0E_GPIO_05_IS_OUTPUT		0
+#define PP_HWID_0E_GPIO_05_IS_OPEN_DRAIN	0
+#define PP_HWID_0E_GPIO_05_OUTPUT_VALUE		0
+#define PP_HWID_0E_GPIO_05_IS_GPIO		1
+#endif
+
+/* GPIO 8: FPGA_TMS */
+#define PP_HWID_0E_GPIO_08_IS_OUTPUT		1
+#define PP_HWID_0E_GPIO_08_IS_OPEN_DRAIN	1
+#define PP_HWID_0E_GPIO_08_OUTPUT_VALUE		1
+#define PP_HWID_0E_GPIO_08_IS_GPIO		1
+
+#if defined(PRODUCT_FLASHX4)
+
+/* GPIO 6: flash prog switch 1 */
+#define PP_HWID_0E_GPIO_06_IS_OUTPUT		0
+#define PP_HWID_0E_GPIO_06_IS_OPEN_DRAIN	0
+#define PP_HWID_0E_GPIO_06_OUTPUT_VALUE		0
+#define PP_HWID_0E_GPIO_06_IS_GPIO		1
+
+/* GPIO 7: flash prog switch 2 */
+#define PP_HWID_0E_GPIO_07_IS_OUTPUT		0
+#define PP_HWID_0E_GPIO_07_IS_OPEN_DRAIN	0
+#define PP_HWID_0E_GPIO_07_OUTPUT_VALUE		0
+#define PP_HWID_0E_GPIO_07_IS_GPIO		1
+
+/* GPIO 9: flash prog switch 4 */
+#define PP_HWID_0E_GPIO_09_IS_OUTPUT		0
+#define PP_HWID_0E_GPIO_09_IS_OPEN_DRAIN	0
+#define PP_HWID_0E_GPIO_09_OUTPUT_VALUE		0
+#define PP_HWID_0E_GPIO_09_IS_GPIO		1
+
+#else /* PRODUCT_FLASHX4 */
+
+/* GPIO 6: Host RST */
+#define PP_HWID_0E_GPIO_06_IS_OUTPUT		1
+#define PP_HWID_0E_GPIO_06_IS_OPEN_DRAIN	0
+#define PP_HWID_0E_GPIO_06_OUTPUT_VALUE		0
+#define PP_HWID_0E_GPIO_06_IS_GPIO		1
+
+/* GPIO 7: Host ATX */
+#define PP_HWID_0E_GPIO_07_IS_OUTPUT		1
+#define PP_HWID_0E_GPIO_07_IS_OPEN_DRAIN	0
+#define PP_HWID_0E_GPIO_07_OUTPUT_VALUE		0
+#define PP_HWID_0E_GPIO_07_IS_GPIO		1
+
+/* GPIO 9: LED2 / Active low */
+#define PP_HWID_0E_GPIO_09_IS_OUTPUT		1
+#define PP_HWID_0E_GPIO_09_IS_OPEN_DRAIN	0
+#define PP_HWID_0E_GPIO_09_OUTPUT_VALUE		0
+#define PP_HWID_0E_GPIO_09_IS_GPIO		1
+
+#endif /* PRODUCT_FLASHX4 */
+
+/* GPIO 10: Unused */
+#define PP_HWID_0E_GPIO_10_IS_OUTPUT		0
+#define PP_HWID_0E_GPIO_10_IS_OPEN_DRAIN	0
+#define PP_HWID_0E_GPIO_10_OUTPUT_VALUE		0
+#define PP_HWID_0E_GPIO_10_IS_GPIO		0
+
+/* GPIO 11: Unused */
+#define PP_HWID_0E_GPIO_11_IS_OUTPUT		0
+#define PP_HWID_0E_GPIO_11_IS_OPEN_DRAIN	0
+#define PP_HWID_0E_GPIO_11_OUTPUT_VALUE		0
+#define PP_HWID_0E_GPIO_11_IS_GPIO		0
+
+/* GPIO 12: Unused */
+#define PP_HWID_0E_GPIO_12_IS_OUTPUT		0
+#define PP_HWID_0E_GPIO_12_IS_OPEN_DRAIN	0
+#define PP_HWID_0E_GPIO_12_OUTPUT_VALUE		0
+#define PP_HWID_0E_GPIO_12_IS_GPIO		0
+
+/* GPIO 13: Unused */
+#define PP_HWID_0E_GPIO_13_IS_OUTPUT		0
+#define PP_HWID_0E_GPIO_13_IS_OPEN_DRAIN	0
+#define PP_HWID_0E_GPIO_13_OUTPUT_VALUE		0
+#define PP_HWID_0E_GPIO_13_IS_GPIO		0
+
+/* GPIO 14: Unused */
+#define PP_HWID_0E_GPIO_14_IS_OUTPUT		0
+#define PP_HWID_0E_GPIO_14_IS_OPEN_DRAIN	0
+#define PP_HWID_0E_GPIO_14_OUTPUT_VALUE		0
+#define PP_HWID_0E_GPIO_14_IS_GPIO		0
+
+/* GPIO 15: Unused */
+#define PP_HWID_0E_GPIO_15_IS_OUTPUT		0
+#define PP_HWID_0E_GPIO_15_IS_OPEN_DRAIN	0
+#define PP_HWID_0E_GPIO_15_OUTPUT_VALUE		0
+#define PP_HWID_0E_GPIO_15_IS_GPIO		0
+
+/* GPIO 16: Unused */
+#define PP_HWID_0E_GPIO_16_IS_OUTPUT		0
+#define PP_HWID_0E_GPIO_16_IS_OPEN_DRAIN	0
+#define PP_HWID_0E_GPIO_16_OUTPUT_VALUE		0
+#define PP_HWID_0E_GPIO_16_IS_GPIO		0
+
+/* GPIO 17: Unused */
+#define PP_HWID_0E_GPIO_17_IS_OUTPUT		0
+#define PP_HWID_0E_GPIO_17_IS_OPEN_DRAIN	0
+#define PP_HWID_0E_GPIO_17_OUTPUT_VALUE		0
+#define PP_HWID_0E_GPIO_17_IS_GPIO		0
+
+/* GPIO 18: Unused */
+#define PP_HWID_0E_GPIO_18_IS_OUTPUT		0
+#define PP_HWID_0E_GPIO_18_IS_OPEN_DRAIN	0
+#define PP_HWID_0E_GPIO_18_OUTPUT_VALUE		0
+#define PP_HWID_0E_GPIO_18_IS_GPIO		0
+
+/* GPIO 19: A/D ATMEL_MOSI */
+#define PP_HWID_0E_GPIO_19_IS_OUTPUT		1
+#define PP_HWID_0E_GPIO_19_IS_OPEN_DRAIN	0
+#define PP_HWID_0E_GPIO_19_OUTPUT_VALUE		0
+#define PP_HWID_0E_GPIO_19_IS_GPIO		1
+
+/* GPIO 20: FPGA_TDO */
+#define PP_HWID_0E_GPIO_20_IS_OUTPUT		0
+#define PP_HWID_0E_GPIO_20_IS_OPEN_DRAIN	0
+#define PP_HWID_0E_GPIO_20_OUTPUT_VALUE		0
+#define PP_HWID_0E_GPIO_20_IS_GPIO		1
+
+/* GPIO 21: A/D ATMEL_MISO */
+#define PP_HWID_0E_GPIO_21_IS_OUTPUT		1
+#define PP_HWID_0E_GPIO_21_IS_OPEN_DRAIN	0
+#define PP_HWID_0E_GPIO_21_OUTPUT_VALUE		0
+#define PP_HWID_0E_GPIO_21_IS_GPIO		1
+
+/* GPIO 22: Unused */
+#define PP_HWID_0E_GPIO_22_IS_OUTPUT		0
+#define PP_HWID_0E_GPIO_22_IS_OPEN_DRAIN	0
+#define PP_HWID_0E_GPIO_22_OUTPUT_VALUE		0
+#define PP_HWID_0E_GPIO_22_IS_GPIO		0
+
+#if PP_FEAT_AD_ATMEL 
+/* GPIO 23: A/D ATMEL_SCK */
+#define PP_HWID_0E_GPIO_23_IS_OUTPUT		1
+#define PP_HWID_0E_GPIO_23_IS_OPEN_DRAIN	0
+#define PP_HWID_0E_GPIO_23_OUTPUT_VALUE		0
+#define PP_HWID_0E_GPIO_23_IS_GPIO		1
+#else
+/* GPIO 23: EXT_POWER, external power supply
+	    for LARA express */
+#define PP_HWID_0E_GPIO_23_IS_OUTPUT		0
+#define PP_HWID_0E_GPIO_23_IS_OPEN_DRAIN	0
+#define PP_HWID_0E_GPIO_23_OUTPUT_VALUE		0
+#define PP_HWID_0E_GPIO_23_IS_GPIO		1
+#endif
+
+/* GPIO 24: Unused */
+#define PP_HWID_0E_GPIO_24_IS_OUTPUT		0
+#define PP_HWID_0E_GPIO_24_IS_OPEN_DRAIN	0
+#define PP_HWID_0E_GPIO_24_OUTPUT_VALUE		0
+#define PP_HWID_0E_GPIO_24_IS_GPIO		0
+
+/* GPIO 25: Unused */
+#define PP_HWID_0E_GPIO_25_IS_OUTPUT		0
+#define PP_HWID_0E_GPIO_25_IS_OPEN_DRAIN	0
+#define PP_HWID_0E_GPIO_25_OUTPUT_VALUE		0
+#define PP_HWID_0E_GPIO_25_IS_GPIO		0
+
+/* GPIO 26: Unused */
+#define PP_HWID_0E_GPIO_26_IS_OUTPUT		0
+#define PP_HWID_0E_GPIO_26_IS_OPEN_DRAIN	0
+#define PP_HWID_0E_GPIO_26_OUTPUT_VALUE		0
+#define PP_HWID_0E_GPIO_26_IS_GPIO		0
+
+/* GPIO 27: Unused */
+#define PP_HWID_0E_GPIO_27_IS_OUTPUT		0
+#define PP_HWID_0E_GPIO_27_IS_OPEN_DRAIN	0
+#define PP_HWID_0E_GPIO_27_OUTPUT_VALUE		0
+#define PP_HWID_0E_GPIO_27_IS_GPIO		0
+
+/* GPIO 28: Unused */
+#define PP_HWID_0E_GPIO_28_IS_OUTPUT		0
+#define PP_HWID_0E_GPIO_28_IS_OPEN_DRAIN	0
+#define PP_HWID_0E_GPIO_28_OUTPUT_VALUE		0
+#define PP_HWID_0E_GPIO_28_IS_GPIO		0
+
+/* GPIO 29: Unused */
+#define PP_HWID_0E_GPIO_29_IS_OUTPUT		0
+#define PP_HWID_0E_GPIO_29_IS_OPEN_DRAIN	0
+#define PP_HWID_0E_GPIO_29_OUTPUT_VALUE		0
+#define PP_HWID_0E_GPIO_29_IS_GPIO		0
+
+/* GPIO 30: Unused */
+#define PP_HWID_0E_GPIO_30_IS_OUTPUT		0
+#define PP_HWID_0E_GPIO_30_IS_OPEN_DRAIN	0
+#define PP_HWID_0E_GPIO_30_OUTPUT_VALUE		0
+#define PP_HWID_0E_GPIO_30_IS_GPIO		0
+
+/* GPIO 31: Unused */
+#define PP_HWID_0E_GPIO_31_IS_OUTPUT		0
+#define PP_HWID_0E_GPIO_31_IS_OPEN_DRAIN	0
+#define PP_HWID_0E_GPIO_31_OUTPUT_VALUE		0
+#define PP_HWID_0E_GPIO_31_IS_GPIO		0
+
+/* ----------------------------------------------------------------------------
+ * External IRQ configuration
+ */
+
+/* USB_IRQ */
+#define PP_HWID_0E_EXT_IRQ_00_HAS_POS_POLARITY	0
+#define PP_HWID_0E_EXT_IRQ_00_IS_EDGE_TRIGGERED	0
+
+/* PHY_IRQ */
+#define PP_HWID_0E_EXT_IRQ_01_HAS_POS_POLARITY	0
+#define PP_HWID_0E_EXT_IRQ_01_IS_EDGE_TRIGGERED	0
+
+/* flash programmer switches */
+#define PP_HWID_0E_EXT_IRQ_02_HAS_POS_POLARITY	0
+#define PP_HWID_0E_EXT_IRQ_02_IS_EDGE_TRIGGERED	1
+
+/* Used as GPIO(20) */
+#define PP_HWID_0E_EXT_IRQ_03_HAS_POS_POLARITY	0
+#define PP_HWID_0E_EXT_IRQ_03_IS_EDGE_TRIGGERED	0
+
+/* Unused */
+#define PP_HWID_0E_EXT_IRQ_04_HAS_POS_POLARITY	0
+#define PP_HWID_0E_EXT_IRQ_04_IS_EDGE_TRIGGERED	0
+
+/* VSC_IRQ */
+#define PP_HWID_0E_EXT_IRQ_05_HAS_POS_POLARITY	0
+#define PP_HWID_0E_EXT_IRQ_05_IS_EDGE_TRIGGERED	0
+
+/* Used as GPIO(23) */
+#define PP_HWID_0E_EXT_IRQ_06_HAS_POS_POLARITY	0
+#define PP_HWID_0E_EXT_IRQ_06_IS_EDGE_TRIGGERED	0
+
+/* ----------------------------------------------------------------------------
+ * Chip Select configuration
+ */
+
+/* ---- Bank 0: Flash ---- */
+
+#define PP_HWID_0E_CS_00_AP_BME		0x1	/* Burst mode enabled (1 bit) */
+#define PP_HWID_0E_CS_00_AP_FWT		0x6	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_0E_CS_00_AP_BWT		0x6	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_0E_CS_00_AP_TWT		0x0	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_0E_CS_00_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_0E_CS_00_AP_OEN		0x1	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_0E_CS_00_AP_WBN		0x1	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_0E_CS_00_AP_WBF		0x1	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_0E_CS_00_AP_TH		0x2	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_0E_CS_00_AP_RE		0x0	/* Ready Enable (1 bit) */
+#define PP_HWID_0E_CS_00_AP_SOR		0x1	/* Sample on Ready (1 bit) */
+#define PP_HWID_0E_CS_00_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_0E_CS_00_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_0E_CS_00_CR_BAS		0xFF800000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_0E_CS_00_CR_BS		0x3
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_0E_CS_00_CR_BU		0x3
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_0E_CS_00_CR_BW		0x1
+
+/* ---- Bank 1: USB ---- */
+
+/*
+ * NOTE: The USB chip has PerRW connected to its WR_N pin. This is wrong.
+ *       As a workaround we set the hold time to 0.
+ */
+
+#define PP_HWID_0E_CS_01_AP_BME		0x0	/* Burst mode enabled (1 bit) */
+#define PP_HWID_0E_CS_01_AP_FWT		0x0	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_0E_CS_01_AP_BWT		0x0	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_0E_CS_01_AP_TWT		0x5	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_0E_CS_01_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_0E_CS_01_AP_OEN		0x1	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_0E_CS_01_AP_WBN		0x1	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_0E_CS_01_AP_WBF		0x1	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_0E_CS_01_AP_TH		0x0	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_0E_CS_01_AP_RE		0x0	/* Ready Enable (1 bit) */
+#define PP_HWID_0E_CS_01_AP_SOR		0x1	/* Sample on Ready (1 bit) */
+#define PP_HWID_0E_CS_01_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_0E_CS_01_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_0E_CS_01_CR_BAS		0xF0000000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_0E_CS_01_CR_BS		0x0
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_0E_CS_01_CR_BU		0x3
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_0E_CS_01_CR_BW		0x1
+
+/* ---- Bank 2: Hardware-ID ---- */
+
+#define PP_HWID_0E_CS_02_AP_BME		0x0	/* Burst mode enabled (1 bit) */
+#define PP_HWID_0E_CS_02_AP_FWT		0x0	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_0E_CS_02_AP_BWT		0x0	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_0E_CS_02_AP_TWT		0x8	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_0E_CS_02_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_0E_CS_02_AP_OEN		0x1	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_0E_CS_02_AP_WBN		0x1	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_0E_CS_02_AP_WBF		0x1	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_0E_CS_02_AP_TH		0x2	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_0E_CS_02_AP_RE		0x0	/* Ready Enable (1 bit) */
+#define PP_HWID_0E_CS_02_AP_SOR		0x1	/* Sample on Ready (1 bit) */
+#define PP_HWID_0E_CS_02_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_0E_CS_02_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_0E_CS_02_CR_BAS		0xF0600000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_0E_CS_02_CR_BS		0x0
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_0E_CS_02_CR_BU		0x3
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_0E_CS_02_CR_BW		0x0
+
+/* ---- Bank 3: Unused ---- */
+
+#define PP_HWID_0E_CS_03_AP_BME		0x0	/* Burst mode enabled (1 bit) */
+#define PP_HWID_0E_CS_03_AP_FWT		0x0	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_0E_CS_03_AP_BWT		0x0	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_0E_CS_03_AP_TWT		0x0	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_0E_CS_03_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_0E_CS_03_AP_OEN		0x0	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_0E_CS_03_AP_WBN		0x0	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_0E_CS_03_AP_WBF		0x0	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_0E_CS_03_AP_TH		0x0	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_0E_CS_03_AP_RE		0x0	/* Ready Enable (1 bit) */
+#define PP_HWID_0E_CS_03_AP_SOR		0x0	/* Sample on Ready (1 bit) */
+#define PP_HWID_0E_CS_03_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_0E_CS_03_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_0E_CS_03_CR_BAS		0x00000000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_0E_CS_03_CR_BS		0x0
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_0E_CS_03_CR_BU		0x0
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_0E_CS_03_CR_BW		0x0
+
+#if defined(PRODUCT_FLASHX4)
+/* ---- Bank 4: Flash Memory for Programmer ---- */
+
+#define PP_HWID_0E_CS_04_AP_BME		0x1	/* Burst mode enabled (1 bit) */
+#define PP_HWID_0E_CS_04_AP_FWT		0x6	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_0E_CS_04_AP_BWT		0x6	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_0E_CS_04_AP_TWT		0x0	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_0E_CS_04_AP_CSN		0x2	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_0E_CS_04_AP_OEN		0x1	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_0E_CS_04_AP_WBN		0x1	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_0E_CS_04_AP_WBF		0x1	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_0E_CS_04_AP_TH		0x6	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_0E_CS_04_AP_RE		0x0	/* Ready Enable (1 bit) */
+#define PP_HWID_0E_CS_04_AP_SOR		0x1	/* Sample on Ready (1 bit) */
+#define PP_HWID_0E_CS_04_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_0E_CS_04_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_0E_CS_04_CR_BAS		0xF1000000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_0E_CS_04_CR_BS		0x4
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_0E_CS_04_CR_BU		0x3
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_0E_CS_04_CR_BW		0x1
+
+#else /* PRODUCT_FLASHX4 */
+/* ---- Bank 4: VSC ---- */
+
+#define PP_HWID_0E_CS_04_AP_BME		0x1	/* Burst mode enabled (1 bit) */
+#define PP_HWID_0E_CS_04_AP_FWT		0x0	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_0E_CS_04_AP_BWT		0x0	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_0E_CS_04_AP_TWT		0x0	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_0E_CS_04_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_0E_CS_04_AP_OEN		0x0	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_0E_CS_04_AP_WBN		0x0	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_0E_CS_04_AP_WBF		0x0	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_0E_CS_04_AP_TH		0x0	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_0E_CS_04_AP_RE		0x1	/* Ready Enable (1 bit) */
+#define PP_HWID_0E_CS_04_AP_SOR		0x1	/* Sample on Ready (1 bit) */
+#define PP_HWID_0E_CS_04_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_0E_CS_04_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_0E_CS_04_CR_BAS		0xF1000000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_0E_CS_04_CR_BS		0x3
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_0E_CS_04_CR_BU		0x3
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_0E_CS_04_CR_BW		0x1
+
+#endif /* PRODUCT_FLASHX4 */
+
+/* ---- Bank 5: Unused ---- */
+
+#define PP_HWID_0E_CS_05_AP_BME		0x0	/* Burst mode enabled (1 bit) */
+#define PP_HWID_0E_CS_05_AP_FWT		0x0	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_0E_CS_05_AP_BWT		0x0	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_0E_CS_05_AP_TWT		0x0	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_0E_CS_05_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_0E_CS_05_AP_OEN		0x0	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_0E_CS_05_AP_WBN		0x0	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_0E_CS_05_AP_WBF		0x0	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_0E_CS_05_AP_TH		0x0	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_0E_CS_05_AP_RE		0x0	/* Ready Enable (1 bit) */
+#define PP_HWID_0E_CS_05_AP_SOR		0x0	/* Sample on Ready (1 bit) */
+#define PP_HWID_0E_CS_05_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_0E_CS_05_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_0E_CS_05_CR_BAS		0x00000000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_0E_CS_05_CR_BS		0x0
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_0E_CS_05_CR_BU		0x0
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_0E_CS_05_CR_BW		0x0
+
+/* ---- Bank 6: unused ---- */
+
+#define PP_HWID_0E_CS_06_AP_BME		0x0	/* Burst mode enabled (1 bit) */
+#define PP_HWID_0E_CS_06_AP_FWT		0x0	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_0E_CS_06_AP_BWT		0x0	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_0E_CS_06_AP_TWT		0x0	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_0E_CS_06_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_0E_CS_06_AP_OEN		0x0	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_0E_CS_06_AP_WBN		0x0	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_0E_CS_06_AP_WBF		0x0	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_0E_CS_06_AP_TH		0x0	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_0E_CS_06_AP_RE		0x0	/* Ready Enable (1 bit) */
+#define PP_HWID_0E_CS_06_AP_SOR		0x0	/* Sample on Ready (1 bit) */
+#define PP_HWID_0E_CS_06_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_0E_CS_06_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_0E_CS_06_CR_BAS		0x00000000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_0E_CS_06_CR_BS		0x0
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_0E_CS_06_CR_BU		0x0
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_0E_CS_06_CR_BW		0x0
+
+/* ---- Bank 7: Unused ---- */
+
+#define PP_HWID_0E_CS_07_AP_BME		0x0	/* Burst mode enabled (1 bit) */
+#define PP_HWID_0E_CS_07_AP_FWT		0x0	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_0E_CS_07_AP_BWT		0x0	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_0E_CS_07_AP_TWT		0x0	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_0E_CS_07_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_0E_CS_07_AP_OEN		0x0	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_0E_CS_07_AP_WBN		0x0	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_0E_CS_07_AP_WBF		0x0	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_0E_CS_07_AP_TH		0x0	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_0E_CS_07_AP_RE		0x0	/* Ready Enable (1 bit) */
+#define PP_HWID_0E_CS_07_AP_SOR		0x0	/* Sample on Ready (1 bit) */
+#define PP_HWID_0E_CS_07_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_0E_CS_07_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_0E_CS_07_CR_BAS		0x00000000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_0E_CS_07_CR_BS		0x0
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_0E_CS_07_CR_BU		0x0
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_0E_CS_07_CR_BW		0x0
+
+/* ----------------------------------------------------------------------------
+ * EBC configuration register
+ */
+#define PP_HWID_0E_EBC_CFG_EBTC		0x1	/* ECB Three-State Control (1 bit) */
+#define PP_HWID_0E_EBC_CFG_PTD		0x0	/* Device-Paced Time-out Disable (1 bit) */
+#define PP_HWID_0E_EBC_CFG_RTC		0x3	/* Ready Timeout Count when PTD=0 (3 bit) */
+#define PP_HWID_0E_EBC_CFG_EMPL		0x0	/* External Master Priority Low (2 bit) */
+#define PP_HWID_0E_EBC_CFG_EMPH		0x0	/* External Master Priority High (2 bit) */
+#define PP_HWID_0E_EBC_CFG_CSTC		0x1	/* Chip Select Three-State Control (1 bit) */
+#define PP_HWID_0E_EBC_CFG_BPF		0x2	/* Burst Prefetch (2 bit) */
+#define PP_HWID_0E_EBC_CFG_EMS		0x0	/* External Master Size (2 bit) */
+#define PP_HWID_0E_EBC_CFG_PME		0x0	/* Power Management Enable (1 bit) */
+#define PP_HWID_0E_EBC_CFG_PMT		0x0	/* Power Management Timer (5 bit) */
+
+#endif /* _HW_0E_H */
Index: board/peppercon/hw_0F.h
===================================================================
RCS file: board/peppercon/hw_0F.h
diff -N board/peppercon/hw_0F.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ board/peppercon/hw_0F.h	29 Apr 2005 08:43:29 -0000	1.2
@@ -0,0 +1,572 @@
+/******************************************************************************
+ *
+ * Hardware configuration of KIM 1.3 / MB "B52" / 16 MB Flash
+ *
+ * Hardware-ID: 0x0F
+ *
+ */  
+
+#ifndef _HW_0F_H
+#define _HW_0F_H
+
+/* ----------------------------------------------------------------------------
+ * Miscellaneous Hardware Configuration
+ */
+
+#define PP_HWID_0F_CPU_TYPE		PP_CPU_405EP	/* The CPU type */
+#define PP_HWID_0F_FLASH_SIZE		(16*1024*1024)	/* Flash size in bytes */
+#define PP_HWID_0F_SDRAM_ROWS		4096		/* SDRAM row count */
+#define PP_HWID_0F_SDRAM_B0CR		0x00062001	/* 32MB @ 0x0 12x9x4 */
+#define PP_HWID_0F_SDRAM_RTR		0x0618		/* 100 MHz; 64ms; 4k refresh */
+#define PP_HWID_0F_SDRAM_TR		0x0086400D	/* 100 MHz; CASL=2, PTA=2, CTP=3, LDF=2, RFTA=7, RCD=2 */
+#define PP_HWID_0F_SYS_CLK_FREQ		33333333	/* external frequency to PLL */
+#define PP_HWID_0F_PHY_LED_CFG_VALUE	0x0472		/* LXT972A; register 0x14 */
+#define PP_HWID_0F_BIGPHYSAREA_PAGES	980		/* # of reserved pages for linux */
+#define PP_HWID_0F_CONSOLE              PP_SERIAL_0
+
+/* ----------------------------------------------------------------------------
+ * The PLL configuration (see PPC405EP manual section 7.2, 7.5.3 and 7.5.4)
+ */
+
+#define PP_HWID_0F_DYNAMIC_PLL	   0
+
+/* ------------- 33 MHz SysClk Settings --------------- */
+/* Slow (66 MHz CPU-Clk) */
+#define PP_HWID_0F_PLLMR0_SLOW (PLL_CPUDIV_2		\
+				   | PLL_PLBDIV_1	\
+				   | PLL_OPBDIV_2	\
+				   | PLL_EXTBUSDIV_2	\
+				   | PLL_MALDIV_1	\
+				   | PLL_PCIDIV_4)
+
+#define PP_HWID_0F_PLLMR1_SLOW (PLL_FBKDIV_6		\
+				   | PLL_FWDDIVA_4	\
+				   | PLL_FWDDIVB_4	\
+				   | PLL_TUNE_15_M_40	\
+				   | PLL_TUNE_VCO_LOW)
+
+/* Fast (200 MHz CPU-Clk) */
+#define PP_HWID_0F_PLLMR0_FAST (PLL_CPUDIV_1		\
+				   | PLL_PLBDIV_2	\
+				   | PLL_OPBDIV_2	\
+				   | PLL_EXTBUSDIV_2	\
+				   | PLL_MALDIV_1	\
+				   | PLL_PCIDIV_3)
+
+
+#define PP_HWID_0F_PLLMR1_FAST (PLL_FBKDIV_6		\
+				   | PLL_FWDDIVA_4	\
+				   | PLL_FWDDIVB_4	\
+				   | PLL_TUNE_15_M_40	\
+				   | PLL_TUNE_VCO_LOW)
+					
+#define PP_HWID_0F_PLLMR0_DEFAULT	PP_HWID_0F_PLLMR0_FAST
+#define PP_HWID_0F_PLLMR1_DEFAULT	PP_HWID_0F_PLLMR1_FAST
+
+/* ----------------------------------------------------------------------------
+ * GPIO configuration
+ */
+
+/* GPIO 0: Unused */
+#define PP_HWID_0F_GPIO_00_IS_OUTPUT		0
+#define PP_HWID_0F_GPIO_00_IS_OPEN_DRAIN	0
+#define PP_HWID_0F_GPIO_00_OUTPUT_VALUE		0
+#define PP_HWID_0F_GPIO_00_IS_GPIO		0
+
+/* GPIO 1: ATMEL_MISO */
+#define PP_HWID_0F_GPIO_01_IS_OUTPUT		0
+#define PP_HWID_0F_GPIO_01_IS_OPEN_DRAIN	0
+#define PP_HWID_0F_GPIO_01_OUTPUT_VALUE		0
+#define PP_HWID_0F_GPIO_01_IS_GPIO		1
+
+/* GPIO 2: ATMEL MOSI / FPGA_TDI */
+#define PP_HWID_0F_GPIO_02_IS_OUTPUT		1
+#define PP_HWID_0F_GPIO_02_IS_OPEN_DRAIN	0
+#define PP_HWID_0F_GPIO_02_OUTPUT_VALUE		0
+#define PP_HWID_0F_GPIO_02_IS_GPIO		1
+
+/* GPIO 3: ATMEL_RST */
+#define PP_HWID_0F_GPIO_03_IS_OUTPUT		1
+#define PP_HWID_0F_GPIO_03_IS_OPEN_DRAIN	0
+#define PP_HWID_0F_GPIO_03_OUTPUT_VALUE		0
+#define PP_HWID_0F_GPIO_03_IS_GPIO		1
+
+/* GPIO 4: ATMEL_SCK / FPGA_TCK */
+#define PP_HWID_0F_GPIO_04_IS_OUTPUT		1
+#define PP_HWID_0F_GPIO_04_IS_OPEN_DRAIN	0
+#define PP_HWID_0F_GPIO_04_OUTPUT_VALUE		0
+#define PP_HWID_0F_GPIO_04_IS_GPIO		1
+
+/* GPIO 5: Default Jumper */
+#define PP_HWID_0F_GPIO_05_IS_OUTPUT		0
+#define PP_HWID_0F_GPIO_05_IS_OPEN_DRAIN	0
+#define PP_HWID_0F_GPIO_05_OUTPUT_VALUE		0
+#define PP_HWID_0F_GPIO_05_IS_GPIO		1
+
+/* GPIO 8: FPGA_TMS */
+#define PP_HWID_0F_GPIO_08_IS_OUTPUT		1
+#define PP_HWID_0F_GPIO_08_IS_OPEN_DRAIN	1
+#define PP_HWID_0F_GPIO_08_OUTPUT_VALUE		1
+#define PP_HWID_0F_GPIO_08_IS_GPIO		1
+
+#if defined(PRODUCT_FLASHX4)
+
+/* GPIO 6: flash prog switch 1 */
+#define PP_HWID_0F_GPIO_06_IS_OUTPUT		0
+#define PP_HWID_0F_GPIO_06_IS_OPEN_DRAIN	0
+#define PP_HWID_0F_GPIO_06_OUTPUT_VALUE		0
+#define PP_HWID_0F_GPIO_06_IS_GPIO		1
+
+/* GPIO 7: flash prog switch 2 */
+#define PP_HWID_0F_GPIO_07_IS_OUTPUT		0
+#define PP_HWID_0F_GPIO_07_IS_OPEN_DRAIN	0
+#define PP_HWID_0F_GPIO_07_OUTPUT_VALUE		0
+#define PP_HWID_0F_GPIO_07_IS_GPIO		1
+
+/* GPIO 9: flash prog switch 4 */
+#define PP_HWID_0F_GPIO_09_IS_OUTPUT		0
+#define PP_HWID_0F_GPIO_09_IS_OPEN_DRAIN	0
+#define PP_HWID_0F_GPIO_09_OUTPUT_VALUE		0
+#define PP_HWID_0F_GPIO_09_IS_GPIO		1
+
+#else /* PRODUCT_FLASHX4 */
+
+/* GPIO 6: Host RST */
+#define PP_HWID_0F_GPIO_06_IS_OUTPUT		1
+#define PP_HWID_0F_GPIO_06_IS_OPEN_DRAIN	0
+#define PP_HWID_0F_GPIO_06_OUTPUT_VALUE		0
+#define PP_HWID_0F_GPIO_06_IS_GPIO		1
+
+/* GPIO 7: Host ATX */
+#define PP_HWID_0F_GPIO_07_IS_OUTPUT		1
+#define PP_HWID_0F_GPIO_07_IS_OPEN_DRAIN	0
+#define PP_HWID_0F_GPIO_07_OUTPUT_VALUE		0
+#define PP_HWID_0F_GPIO_07_IS_GPIO		1
+
+/* GPIO 9: LED2 / Active low */
+#define PP_HWID_0F_GPIO_09_IS_OUTPUT		1
+#define PP_HWID_0F_GPIO_09_IS_OPEN_DRAIN	0
+#define PP_HWID_0F_GPIO_09_OUTPUT_VALUE		0
+#define PP_HWID_0F_GPIO_09_IS_GPIO		1
+
+#endif /* PRODUCT_FLASHX4 */
+
+/* GPIO 10: Unused */
+#define PP_HWID_0F_GPIO_10_IS_OUTPUT		0
+#define PP_HWID_0F_GPIO_10_IS_OPEN_DRAIN	0
+#define PP_HWID_0F_GPIO_10_OUTPUT_VALUE		0
+#define PP_HWID_0F_GPIO_10_IS_GPIO		0
+
+/* GPIO 11: Unused */
+#define PP_HWID_0F_GPIO_11_IS_OUTPUT		0
+#define PP_HWID_0F_GPIO_11_IS_OPEN_DRAIN	0
+#define PP_HWID_0F_GPIO_11_OUTPUT_VALUE		0
+#define PP_HWID_0F_GPIO_11_IS_GPIO		0
+
+/* GPIO 12: Unused */
+#define PP_HWID_0F_GPIO_12_IS_OUTPUT		0
+#define PP_HWID_0F_GPIO_12_IS_OPEN_DRAIN	0
+#define PP_HWID_0F_GPIO_12_OUTPUT_VALUE		0
+#define PP_HWID_0F_GPIO_12_IS_GPIO		0
+
+/* GPIO 13: Unused */
+#define PP_HWID_0F_GPIO_13_IS_OUTPUT		0
+#define PP_HWID_0F_GPIO_13_IS_OPEN_DRAIN	0
+#define PP_HWID_0F_GPIO_13_OUTPUT_VALUE		0
+#define PP_HWID_0F_GPIO_13_IS_GPIO		0
+
+/* GPIO 14: Unused */
+#define PP_HWID_0F_GPIO_14_IS_OUTPUT		0
+#define PP_HWID_0F_GPIO_14_IS_OPEN_DRAIN	0
+#define PP_HWID_0F_GPIO_14_OUTPUT_VALUE		0
+#define PP_HWID_0F_GPIO_14_IS_GPIO		0
+
+/* GPIO 15: Unused */
+#define PP_HWID_0F_GPIO_15_IS_OUTPUT		0
+#define PP_HWID_0F_GPIO_15_IS_OPEN_DRAIN	0
+#define PP_HWID_0F_GPIO_15_OUTPUT_VALUE		0
+#define PP_HWID_0F_GPIO_15_IS_GPIO		0
+
+/* GPIO 16: Unused */
+#define PP_HWID_0F_GPIO_16_IS_OUTPUT		0
+#define PP_HWID_0F_GPIO_16_IS_OPEN_DRAIN	0
+#define PP_HWID_0F_GPIO_16_OUTPUT_VALUE		0
+#define PP_HWID_0F_GPIO_16_IS_GPIO		0
+
+/* GPIO 17: Unused */
+#define PP_HWID_0F_GPIO_17_IS_OUTPUT		0
+#define PP_HWID_0F_GPIO_17_IS_OPEN_DRAIN	0
+#define PP_HWID_0F_GPIO_17_OUTPUT_VALUE		0
+#define PP_HWID_0F_GPIO_17_IS_GPIO		0
+
+/* GPIO 18: Unused */
+#define PP_HWID_0F_GPIO_18_IS_OUTPUT		0
+#define PP_HWID_0F_GPIO_18_IS_OPEN_DRAIN	0
+#define PP_HWID_0F_GPIO_18_OUTPUT_VALUE		0
+#define PP_HWID_0F_GPIO_18_IS_GPIO		0
+
+/* GPIO 19: Unused */
+#define PP_HWID_0F_GPIO_19_IS_OUTPUT		0
+#define PP_HWID_0F_GPIO_19_IS_OPEN_DRAIN	0
+#define PP_HWID_0F_GPIO_19_OUTPUT_VALUE		0
+#define PP_HWID_0F_GPIO_19_IS_GPIO		0
+
+/* GPIO 20: FPGA_TDO */
+#define PP_HWID_0F_GPIO_20_IS_OUTPUT		0
+#define PP_HWID_0F_GPIO_20_IS_OPEN_DRAIN	0
+#define PP_HWID_0F_GPIO_20_OUTPUT_VALUE		0
+#define PP_HWID_0F_GPIO_20_IS_GPIO		1
+
+/* GPIO 21: Unused */
+#define PP_HWID_0F_GPIO_21_IS_OUTPUT		0
+#define PP_HWID_0F_GPIO_21_IS_OPEN_DRAIN	0
+#define PP_HWID_0F_GPIO_21_OUTPUT_VALUE		0
+#define PP_HWID_0F_GPIO_21_IS_GPIO		0
+
+/* GPIO 22: Unused */
+#define PP_HWID_0F_GPIO_22_IS_OUTPUT		0
+#define PP_HWID_0F_GPIO_22_IS_OPEN_DRAIN	0
+#define PP_HWID_0F_GPIO_22_OUTPUT_VALUE		0
+#define PP_HWID_0F_GPIO_22_IS_GPIO		0
+
+/* GPIO 23: EXT_POWER, external power supply
+	    for LARA express */
+#define PP_HWID_0F_GPIO_23_IS_OUTPUT		0
+#define PP_HWID_0F_GPIO_23_IS_OPEN_DRAIN	0
+#define PP_HWID_0F_GPIO_23_OUTPUT_VALUE		0
+#define PP_HWID_0F_GPIO_23_IS_GPIO		1
+
+/* GPIO 24: Unused */
+#define PP_HWID_0F_GPIO_24_IS_OUTPUT		0
+#define PP_HWID_0F_GPIO_24_IS_OPEN_DRAIN	0
+#define PP_HWID_0F_GPIO_24_OUTPUT_VALUE		0
+#define PP_HWID_0F_GPIO_24_IS_GPIO		0
+
+/* GPIO 25: Unused */
+#define PP_HWID_0F_GPIO_25_IS_OUTPUT		0
+#define PP_HWID_0F_GPIO_25_IS_OPEN_DRAIN	0
+#define PP_HWID_0F_GPIO_25_OUTPUT_VALUE		0
+#define PP_HWID_0F_GPIO_25_IS_GPIO		0
+
+/* GPIO 26: Unused */
+#define PP_HWID_0F_GPIO_26_IS_OUTPUT		0
+#define PP_HWID_0F_GPIO_26_IS_OPEN_DRAIN	0
+#define PP_HWID_0F_GPIO_26_OUTPUT_VALUE		0
+#define PP_HWID_0F_GPIO_26_IS_GPIO		0
+
+/* GPIO 27: Unused */
+#define PP_HWID_0F_GPIO_27_IS_OUTPUT		0
+#define PP_HWID_0F_GPIO_27_IS_OPEN_DRAIN	0
+#define PP_HWID_0F_GPIO_27_OUTPUT_VALUE		0
+#define PP_HWID_0F_GPIO_27_IS_GPIO		0
+
+/* GPIO 28: Unused */
+#define PP_HWID_0F_GPIO_28_IS_OUTPUT		0
+#define PP_HWID_0F_GPIO_28_IS_OPEN_DRAIN	0
+#define PP_HWID_0F_GPIO_28_OUTPUT_VALUE		0
+#define PP_HWID_0F_GPIO_28_IS_GPIO		0
+
+/* GPIO 29: Unused */
+#define PP_HWID_0F_GPIO_29_IS_OUTPUT		0
+#define PP_HWID_0F_GPIO_29_IS_OPEN_DRAIN	0
+#define PP_HWID_0F_GPIO_29_OUTPUT_VALUE		0
+#define PP_HWID_0F_GPIO_29_IS_GPIO		0
+
+/* GPIO 30: Unused */
+#define PP_HWID_0F_GPIO_30_IS_OUTPUT		0
+#define PP_HWID_0F_GPIO_30_IS_OPEN_DRAIN	0
+#define PP_HWID_0F_GPIO_30_OUTPUT_VALUE		0
+#define PP_HWID_0F_GPIO_30_IS_GPIO		0
+
+/* GPIO 31: Unused */
+#define PP_HWID_0F_GPIO_31_IS_OUTPUT		0
+#define PP_HWID_0F_GPIO_31_IS_OPEN_DRAIN	0
+#define PP_HWID_0F_GPIO_31_OUTPUT_VALUE		0
+#define PP_HWID_0F_GPIO_31_IS_GPIO		0
+
+/* ----------------------------------------------------------------------------
+ * External IRQ configuration
+ */
+
+/* USB_IRQ */
+#define PP_HWID_0F_EXT_IRQ_00_HAS_POS_POLARITY	0
+#define PP_HWID_0F_EXT_IRQ_00_IS_EDGE_TRIGGERED	0
+
+/* PHY_IRQ */
+#define PP_HWID_0F_EXT_IRQ_01_HAS_POS_POLARITY	0
+#define PP_HWID_0F_EXT_IRQ_01_IS_EDGE_TRIGGERED	0
+
+/* flash programmer switches */
+#define PP_HWID_0F_EXT_IRQ_02_HAS_POS_POLARITY	0
+#define PP_HWID_0F_EXT_IRQ_02_IS_EDGE_TRIGGERED	1
+
+/* Used as GPIO(20) */
+#define PP_HWID_0F_EXT_IRQ_03_HAS_POS_POLARITY	0
+#define PP_HWID_0F_EXT_IRQ_03_IS_EDGE_TRIGGERED	0
+
+/* Unused */
+#define PP_HWID_0F_EXT_IRQ_04_HAS_POS_POLARITY	0
+#define PP_HWID_0F_EXT_IRQ_04_IS_EDGE_TRIGGERED	0
+
+/* VSC_IRQ */
+#define PP_HWID_0F_EXT_IRQ_05_HAS_POS_POLARITY	0
+#define PP_HWID_0F_EXT_IRQ_05_IS_EDGE_TRIGGERED	0
+
+/* Used as GPIO(23) */
+#define PP_HWID_0F_EXT_IRQ_06_HAS_POS_POLARITY	0
+#define PP_HWID_0F_EXT_IRQ_06_IS_EDGE_TRIGGERED	0
+
+/* ----------------------------------------------------------------------------
+ * Chip Select configuration
+ */
+
+/* ---- Bank 0: Flash ---- */
+
+#define PP_HWID_0F_CS_00_AP_BME		0x1	/* Burst mode enabled (1 bit) */
+#define PP_HWID_0F_CS_00_AP_FWT		0x6	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_0F_CS_00_AP_BWT		0x6	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_0F_CS_00_AP_TWT		0x0	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_0F_CS_00_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_0F_CS_00_AP_OEN		0x1	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_0F_CS_00_AP_WBN		0x1	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_0F_CS_00_AP_WBF		0x1	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_0F_CS_00_AP_TH		0x2	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_0F_CS_00_AP_RE		0x0	/* Ready Enable (1 bit) */
+#define PP_HWID_0F_CS_00_AP_SOR		0x1	/* Sample on Ready (1 bit) */
+#define PP_HWID_0F_CS_00_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_0F_CS_00_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_0F_CS_00_CR_BAS		0xFF000000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_0F_CS_00_CR_BS		0x4
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_0F_CS_00_CR_BU		0x3
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_0F_CS_00_CR_BW		0x1
+
+/* ---- Bank 1: USB ---- */
+
+/*
+ * NOTE: The USB chip has PerRW connected to its WR_N pin. This is wrong.
+ *       As a workaround we set the hold time to 0.
+ */
+
+#define PP_HWID_0F_CS_01_AP_BME		0x0	/* Burst mode enabled (1 bit) */
+#define PP_HWID_0F_CS_01_AP_FWT		0x0	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_0F_CS_01_AP_BWT		0x0	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_0F_CS_01_AP_TWT		0x5	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_0F_CS_01_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_0F_CS_01_AP_OEN		0x1	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_0F_CS_01_AP_WBN		0x1	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_0F_CS_01_AP_WBF		0x1	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_0F_CS_01_AP_TH		0x0	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_0F_CS_01_AP_RE		0x0	/* Ready Enable (1 bit) */
+#define PP_HWID_0F_CS_01_AP_SOR		0x1	/* Sample on Ready (1 bit) */
+#define PP_HWID_0F_CS_01_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_0F_CS_01_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_0F_CS_01_CR_BAS		0xF0000000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_0F_CS_01_CR_BS		0x0
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_0F_CS_01_CR_BU		0x3
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_0F_CS_01_CR_BW		0x1
+
+/* ---- Bank 2: Hardware-ID ---- */
+
+#define PP_HWID_0F_CS_02_AP_BME		0x0	/* Burst mode enabled (1 bit) */
+#define PP_HWID_0F_CS_02_AP_FWT		0x0	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_0F_CS_02_AP_BWT		0x0	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_0F_CS_02_AP_TWT		0x8	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_0F_CS_02_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_0F_CS_02_AP_OEN		0x1	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_0F_CS_02_AP_WBN		0x1	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_0F_CS_02_AP_WBF		0x1	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_0F_CS_02_AP_TH		0x2	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_0F_CS_02_AP_RE		0x0	/* Ready Enable (1 bit) */
+#define PP_HWID_0F_CS_02_AP_SOR		0x1	/* Sample on Ready (1 bit) */
+#define PP_HWID_0F_CS_02_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_0F_CS_02_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_0F_CS_02_CR_BAS		0xF0600000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_0F_CS_02_CR_BS		0x0
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_0F_CS_02_CR_BU		0x3
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_0F_CS_02_CR_BW		0x0
+
+/* ---- Bank 3: Unused ---- */
+
+#define PP_HWID_0F_CS_03_AP_BME		0x0	/* Burst mode enabled (1 bit) */
+#define PP_HWID_0F_CS_03_AP_FWT		0x0	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_0F_CS_03_AP_BWT		0x0	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_0F_CS_03_AP_TWT		0x0	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_0F_CS_03_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_0F_CS_03_AP_OEN		0x0	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_0F_CS_03_AP_WBN		0x0	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_0F_CS_03_AP_WBF		0x0	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_0F_CS_03_AP_TH		0x0	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_0F_CS_03_AP_RE		0x0	/* Ready Enable (1 bit) */
+#define PP_HWID_0F_CS_03_AP_SOR		0x0	/* Sample on Ready (1 bit) */
+#define PP_HWID_0F_CS_03_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_0F_CS_03_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_0F_CS_03_CR_BAS		0x00000000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_0F_CS_03_CR_BS		0x0
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_0F_CS_03_CR_BU		0x0
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_0F_CS_03_CR_BW		0x0
+
+#if defined(PRODUCT_FLASHX4)
+/* ---- Bank 4: Flash Memory for Programmer ---- */
+
+#define PP_HWID_0F_CS_04_AP_BME		0x1	/* Burst mode enabled (1 bit) */
+#define PP_HWID_0F_CS_04_AP_FWT		0x6	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_0F_CS_04_AP_BWT		0x6	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_0F_CS_04_AP_TWT		0x0	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_0F_CS_04_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_0F_CS_04_AP_OEN		0x1	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_0F_CS_04_AP_WBN		0x1	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_0F_CS_04_AP_WBF		0x1	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_0F_CS_04_AP_TH		0x2	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_0F_CS_04_AP_RE		0x0	/* Ready Enable (1 bit) */
+#define PP_HWID_0F_CS_04_AP_SOR		0x1	/* Sample on Ready (1 bit) */
+#define PP_HWID_0F_CS_04_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_0F_CS_04_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_0F_CS_04_CR_BAS		0xF1000000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_0F_CS_04_CR_BS		0x3
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_0F_CS_04_CR_BU		0x3
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_0F_CS_04_CR_BW		0x1
+
+#else /* PRODUCT_FLASHX4 */
+/* ---- Bank 4: VSC ---- */
+
+#define PP_HWID_0F_CS_04_AP_BME		0x1	/* Burst mode enabled (1 bit) */
+#define PP_HWID_0F_CS_04_AP_FWT		0x0	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_0F_CS_04_AP_BWT		0x0	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_0F_CS_04_AP_TWT		0x0	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_0F_CS_04_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_0F_CS_04_AP_OEN		0x0	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_0F_CS_04_AP_WBN		0x0	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_0F_CS_04_AP_WBF		0x0	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_0F_CS_04_AP_TH		0x0	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_0F_CS_04_AP_RE		0x1	/* Ready Enable (1 bit) */
+#define PP_HWID_0F_CS_04_AP_SOR		0x1	/* Sample on Ready (1 bit) */
+#define PP_HWID_0F_CS_04_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_0F_CS_04_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_0F_CS_04_CR_BAS		0xF1000000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_0F_CS_04_CR_BS		0x3
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_0F_CS_04_CR_BU		0x3
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_0F_CS_04_CR_BW		0x1
+
+#endif /* PRODUCT_FLASHX4 */
+
+/* ---- Bank 5: Unused ---- */
+
+#define PP_HWID_0F_CS_05_AP_BME		0x0	/* Burst mode enabled (1 bit) */
+#define PP_HWID_0F_CS_05_AP_FWT		0x0	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_0F_CS_05_AP_BWT		0x0	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_0F_CS_05_AP_TWT		0x0	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_0F_CS_05_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_0F_CS_05_AP_OEN		0x0	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_0F_CS_05_AP_WBN		0x0	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_0F_CS_05_AP_WBF		0x0	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_0F_CS_05_AP_TH		0x0	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_0F_CS_05_AP_RE		0x0	/* Ready Enable (1 bit) */
+#define PP_HWID_0F_CS_05_AP_SOR		0x0	/* Sample on Ready (1 bit) */
+#define PP_HWID_0F_CS_05_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_0F_CS_05_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_0F_CS_05_CR_BAS		0x00000000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_0F_CS_05_CR_BS		0x0
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_0F_CS_05_CR_BU		0x0
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_0F_CS_05_CR_BW		0x0
+
+/* ---- Bank 6: unused ---- */
+
+#define PP_HWID_0F_CS_06_AP_BME		0x0	/* Burst mode enabled (1 bit) */
+#define PP_HWID_0F_CS_06_AP_FWT		0x0	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_0F_CS_06_AP_BWT		0x0	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_0F_CS_06_AP_TWT		0x0	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_0F_CS_06_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_0F_CS_06_AP_OEN		0x0	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_0F_CS_06_AP_WBN		0x0	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_0F_CS_06_AP_WBF		0x0	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_0F_CS_06_AP_TH		0x0	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_0F_CS_06_AP_RE		0x0	/* Ready Enable (1 bit) */
+#define PP_HWID_0F_CS_06_AP_SOR		0x0	/* Sample on Ready (1 bit) */
+#define PP_HWID_0F_CS_06_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_0F_CS_06_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_0F_CS_06_CR_BAS		0x00000000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_0F_CS_06_CR_BS		0x0
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_0F_CS_06_CR_BU		0x0
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_0F_CS_06_CR_BW		0x0
+
+/* ---- Bank 7: Unused ---- */
+
+#define PP_HWID_0F_CS_07_AP_BME		0x0	/* Burst mode enabled (1 bit) */
+#define PP_HWID_0F_CS_07_AP_FWT		0x0	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_0F_CS_07_AP_BWT		0x0	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_0F_CS_07_AP_TWT		0x0	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_0F_CS_07_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_0F_CS_07_AP_OEN		0x0	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_0F_CS_07_AP_WBN		0x0	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_0F_CS_07_AP_WBF		0x0	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_0F_CS_07_AP_TH		0x0	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_0F_CS_07_AP_RE		0x0	/* Ready Enable (1 bit) */
+#define PP_HWID_0F_CS_07_AP_SOR		0x0	/* Sample on Ready (1 bit) */
+#define PP_HWID_0F_CS_07_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_0F_CS_07_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_0F_CS_07_CR_BAS		0x00000000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_0F_CS_07_CR_BS		0x0
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_0F_CS_07_CR_BU		0x0
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_0F_CS_07_CR_BW		0x0
+
+/* ----------------------------------------------------------------------------
+ * EBC configuration register
+ */
+
+#define PP_HWID_0F_EBC_CFG_EBTC		0x1	/* ECB Three-State Control (1 bit) */
+#define PP_HWID_0F_EBC_CFG_PTD		0x0	/* Device-Paced Time-out Disable (1 bit) */
+#define PP_HWID_0F_EBC_CFG_RTC		0x3	/* Ready Timeout Count when PTD=0 (3 bit) */
+#define PP_HWID_0F_EBC_CFG_EMPL		0x0	/* External Master Priority Low (2 bit) */
+#define PP_HWID_0F_EBC_CFG_EMPH		0x0	/* External Master Priority High (2 bit) */
+#define PP_HWID_0F_EBC_CFG_CSTC		0x1	/* Chip Select Three-State Control (1 bit) */
+#define PP_HWID_0F_EBC_CFG_BPF		0x2	/* Burst Prefetch (2 bit) */
+#define PP_HWID_0F_EBC_CFG_EMS		0x0	/* External Master Size (2 bit) */
+#define PP_HWID_0F_EBC_CFG_PME		0x0	/* Power Management Enable (1 bit) */
+#define PP_HWID_0F_EBC_CFG_PMT		0x0	/* Power Management Timer (5 bit) */
+
+#endif /* _HW_0F_H */
Index: board/peppercon/hw_10.h
===================================================================
RCS file: board/peppercon/hw_10.h
diff -N board/peppercon/hw_10.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ board/peppercon/hw_10.h	13 May 2005 13:08:58 -0000	1.4
@@ -0,0 +1,520 @@
+/******************************************************************************
+ *
+ * Hardware configuration of MSI KIM-based board
+ *
+ * Hardware-ID: 0x10
+ *
+ */  
+
+#ifndef _HW_10_H
+#define _HW_10_H
+
+/* ----------------------------------------------------------------------------
+ * Miscellaneous Hardware Configuration
+ */
+
+#define PP_HWID_10_CPU_TYPE		PP_CPU_405EP	/* The CPU type */
+#define PP_HWID_10_FLASH_SIZE		(8*1024*1024)	/* Flash size in bytes */
+#define PP_HWID_10_SDRAM_ROWS		4096		/* SDRAM row count */
+#define PP_HWID_10_SDRAM_B0CR		0x00062001	/* 32MB @ 0x0 12x9x4 */
+#define PP_HWID_10_SDRAM_RTR		0x0618		/* 100 MHz; 64ms; 4k refresh */
+#define PP_HWID_10_SDRAM_TR		0x0086400D	/* 100 MHz; CASL=2, PTA=2, CTP=3, LDF=2, RFTA=7, RCD=2 */
+#define PP_HWID_10_SYS_CLK_FREQ		33333333	/* external frequency to PLL */
+#define PP_HWID_10_PHY_LED_CFG_VALUE	0x0472		/* LXT972A; register 0x14 */
+#define PP_HWID_10_BIGPHYSAREA_PAGES	1026		/* # of reserved pages for linux */
+#define PP_HWID_10_CONSOLE              PP_SERIAL_1
+
+#define PP_HWID_10_DESCRIPTION		"MSI KIM 1.2 / MSI MB"
+
+/* ----------------------------------------------------------------------------
+ * The PLL configuration (see PPC405EP manual section 7.2, 7.5.3 and 7.5.4)
+ */
+
+#define PP_HWID_10_DYNAMIC_PLL	   0
+
+/* ------------- 33 MHz SysClk Settings --------------- */
+/* Slow (66 MHz CPU-Clk) */
+#define PP_HWID_10_PLLMR0_SLOW (PLL_CPUDIV_2		\
+				   | PLL_PLBDIV_1	\
+				   | PLL_OPBDIV_2	\
+				   | PLL_EXTBUSDIV_2	\
+				   | PLL_MALDIV_1	\
+				   | PLL_PCIDIV_4)
+
+#define PP_HWID_10_PLLMR1_SLOW (PLL_FBKDIV_6		\
+				   | PLL_FWDDIVA_4	\
+				   | PLL_FWDDIVB_4	\
+				   | PLL_TUNE_15_M_40	\
+				   | PLL_TUNE_VCO_LOW)
+
+/* Fast (200 MHz CPU-Clk, 33 MHz bus) */
+#define PP_HWID_10_PLLMR0_FAST (PLL_CPUDIV_1		\
+				   | PLL_PLBDIV_2	\
+				   | PLL_OPBDIV_2	\
+				   | PLL_EXTBUSDIV_3	\
+				   | PLL_MALDIV_1	\
+				   | PLL_PCIDIV_3)
+
+#define PP_HWID_10_PLLMR1_FAST (PLL_FBKDIV_6		\
+				   | PLL_FWDDIVA_4	\
+				   | PLL_FWDDIVB_4	\
+				   | PLL_TUNE_15_M_40	\
+				   | PLL_TUNE_VCO_LOW)
+					
+#define PP_HWID_10_PLLMR0_DEFAULT	PP_HWID_10_PLLMR0_FAST
+#define PP_HWID_10_PLLMR1_DEFAULT	PP_HWID_10_PLLMR1_FAST
+
+/* ----------------------------------------------------------------------------
+ * GPIO configuration
+ */
+
+/* GPIO 0: Unused */
+#define PP_HWID_10_GPIO_00_IS_OUTPUT		0
+#define PP_HWID_10_GPIO_00_IS_OPEN_DRAIN	0
+#define PP_HWID_10_GPIO_00_OUTPUT_VALUE		0
+#define PP_HWID_10_GPIO_00_IS_GPIO		0
+
+/* GPIO 1: enable TX/RX cross for ttyS0 */
+#define PP_HWID_10_GPIO_01_IS_OUTPUT		1
+#define PP_HWID_10_GPIO_01_IS_OPEN_DRAIN	0
+#define PP_HWID_10_GPIO_01_OUTPUT_VALUE		0
+#define PP_HWID_10_GPIO_01_IS_GPIO		1
+
+/* GPIO 2: ATMEL MOSI / FPGA_TDI */
+#define PP_HWID_10_GPIO_02_IS_OUTPUT		1
+#define PP_HWID_10_GPIO_02_IS_OPEN_DRAIN	0
+#define PP_HWID_10_GPIO_02_OUTPUT_VALUE		0
+#define PP_HWID_10_GPIO_02_IS_GPIO		1
+
+/* GPIO 3: ATMEL_RST */
+#define PP_HWID_10_GPIO_03_IS_OUTPUT		1
+#define PP_HWID_10_GPIO_03_IS_OPEN_DRAIN	0
+#define PP_HWID_10_GPIO_03_OUTPUT_VALUE		0
+#define PP_HWID_10_GPIO_03_IS_GPIO		1
+
+/* GPIO 4: ATMEL_SCK / FPGA_TCK */
+#define PP_HWID_10_GPIO_04_IS_OUTPUT		1
+#define PP_HWID_10_GPIO_04_IS_OPEN_DRAIN	0
+#define PP_HWID_10_GPIO_04_OUTPUT_VALUE		0
+#define PP_HWID_10_GPIO_04_IS_GPIO		1
+
+/* GPIO 5: Default Jumper */
+#define PP_HWID_10_GPIO_05_IS_OUTPUT		0
+#define PP_HWID_10_GPIO_05_IS_OPEN_DRAIN	0
+#define PP_HWID_10_GPIO_05_OUTPUT_VALUE		0
+#define PP_HWID_10_GPIO_05_IS_GPIO		1
+
+/* GPIO 6: Host RST */
+#define PP_HWID_10_GPIO_06_IS_OUTPUT		1
+#define PP_HWID_10_GPIO_06_IS_OPEN_DRAIN	0
+#define PP_HWID_10_GPIO_06_OUTPUT_VALUE		0
+#define PP_HWID_10_GPIO_06_IS_GPIO		1
+
+/* GPIO 7: Host ATX */
+#define PP_HWID_10_GPIO_07_IS_OUTPUT		1
+#define PP_HWID_10_GPIO_07_IS_OPEN_DRAIN	0
+#define PP_HWID_10_GPIO_07_OUTPUT_VALUE		0
+#define PP_HWID_10_GPIO_07_IS_GPIO		1
+
+/* GPIO 8: FPGA_TMS */
+#define PP_HWID_10_GPIO_08_IS_OUTPUT		1
+#define PP_HWID_10_GPIO_08_IS_OPEN_DRAIN	1
+#define PP_HWID_10_GPIO_08_OUTPUT_VALUE		1
+#define PP_HWID_10_GPIO_08_IS_GPIO		1
+
+/* GPIO 9: Chassis RS232 enable */
+#define PP_HWID_10_GPIO_09_IS_OUTPUT		1
+#define PP_HWID_10_GPIO_09_IS_OPEN_DRAIN	0
+#define PP_HWID_10_GPIO_09_OUTPUT_VALUE		1
+#define PP_HWID_10_GPIO_09_IS_GPIO		1
+
+/* GPIO 10: Unused */
+#define PP_HWID_10_GPIO_10_IS_OUTPUT		0
+#define PP_HWID_10_GPIO_10_IS_OPEN_DRAIN	0
+#define PP_HWID_10_GPIO_10_OUTPUT_VALUE		0
+#define PP_HWID_10_GPIO_10_IS_GPIO		0
+
+/* GPIO 11: Unused */
+#define PP_HWID_10_GPIO_11_IS_OUTPUT		0
+#define PP_HWID_10_GPIO_11_IS_OPEN_DRAIN	0
+#define PP_HWID_10_GPIO_11_OUTPUT_VALUE		0
+#define PP_HWID_10_GPIO_11_IS_GPIO		0
+
+/* GPIO 12: Unused */
+#define PP_HWID_10_GPIO_12_IS_OUTPUT		0
+#define PP_HWID_10_GPIO_12_IS_OPEN_DRAIN	0
+#define PP_HWID_10_GPIO_12_OUTPUT_VALUE		0
+#define PP_HWID_10_GPIO_12_IS_GPIO		0
+
+/* GPIO 13: Unused */
+#define PP_HWID_10_GPIO_13_IS_OUTPUT		0
+#define PP_HWID_10_GPIO_13_IS_OPEN_DRAIN	0
+#define PP_HWID_10_GPIO_13_OUTPUT_VALUE		0
+#define PP_HWID_10_GPIO_13_IS_GPIO		0
+
+/* GPIO 14: Unused */
+#define PP_HWID_10_GPIO_14_IS_OUTPUT		0
+#define PP_HWID_10_GPIO_14_IS_OPEN_DRAIN	0
+#define PP_HWID_10_GPIO_14_OUTPUT_VALUE		0
+#define PP_HWID_10_GPIO_14_IS_GPIO		0
+
+/* GPIO 15: Unused */
+#define PP_HWID_10_GPIO_15_IS_OUTPUT		0
+#define PP_HWID_10_GPIO_15_IS_OPEN_DRAIN	0
+#define PP_HWID_10_GPIO_15_OUTPUT_VALUE		0
+#define PP_HWID_10_GPIO_15_IS_GPIO		0
+
+/* GPIO 16: Unused */
+#define PP_HWID_10_GPIO_16_IS_OUTPUT		0
+#define PP_HWID_10_GPIO_16_IS_OPEN_DRAIN	0
+#define PP_HWID_10_GPIO_16_OUTPUT_VALUE		0
+#define PP_HWID_10_GPIO_16_IS_GPIO		0
+
+/* GPIO 17: Unused */
+#define PP_HWID_10_GPIO_17_IS_OUTPUT		0
+#define PP_HWID_10_GPIO_17_IS_OPEN_DRAIN	0
+#define PP_HWID_10_GPIO_17_OUTPUT_VALUE		0
+#define PP_HWID_10_GPIO_17_IS_GPIO		0
+
+/* GPIO 18: Unused */
+#define PP_HWID_10_GPIO_18_IS_OUTPUT		0
+#define PP_HWID_10_GPIO_18_IS_OPEN_DRAIN	0
+#define PP_HWID_10_GPIO_18_OUTPUT_VALUE		0
+#define PP_HWID_10_GPIO_18_IS_GPIO		0
+
+/* GPIO 19: Unused */
+#define PP_HWID_10_GPIO_19_IS_OUTPUT		0
+#define PP_HWID_10_GPIO_19_IS_OPEN_DRAIN	0
+#define PP_HWID_10_GPIO_19_OUTPUT_VALUE		0
+#define PP_HWID_10_GPIO_19_IS_GPIO		0
+
+/* GPIO 20: FPGA_TDO */
+#define PP_HWID_10_GPIO_20_IS_OUTPUT		0
+#define PP_HWID_10_GPIO_20_IS_OPEN_DRAIN	0
+#define PP_HWID_10_GPIO_20_OUTPUT_VALUE		0
+#define PP_HWID_10_GPIO_20_IS_GPIO		1
+
+/* GPIO 21: Unused */
+#define PP_HWID_10_GPIO_21_IS_OUTPUT		0
+#define PP_HWID_10_GPIO_21_IS_OPEN_DRAIN	0
+#define PP_HWID_10_GPIO_21_OUTPUT_VALUE		0
+#define PP_HWID_10_GPIO_21_IS_GPIO		0
+
+/* GPIO 22: Unused */
+#define PP_HWID_10_GPIO_22_IS_OUTPUT		0
+#define PP_HWID_10_GPIO_22_IS_OPEN_DRAIN	0
+#define PP_HWID_10_GPIO_22_OUTPUT_VALUE		0
+#define PP_HWID_10_GPIO_22_IS_GPIO		0
+
+/* GPIO 23: Unused */
+#define PP_HWID_10_GPIO_23_IS_OUTPUT		0
+#define PP_HWID_10_GPIO_23_IS_OPEN_DRAIN	0
+#define PP_HWID_10_GPIO_23_OUTPUT_VALUE		0
+#define PP_HWID_10_GPIO_23_IS_GPIO		0
+
+/* GPIO 24: Unused */
+#define PP_HWID_10_GPIO_24_IS_OUTPUT		0
+#define PP_HWID_10_GPIO_24_IS_OPEN_DRAIN	0
+#define PP_HWID_10_GPIO_24_OUTPUT_VALUE		0
+#define PP_HWID_10_GPIO_24_IS_GPIO		0
+
+/* GPIO 25: Unused */
+#define PP_HWID_10_GPIO_25_IS_OUTPUT		0
+#define PP_HWID_10_GPIO_25_IS_OPEN_DRAIN	0
+#define PP_HWID_10_GPIO_25_OUTPUT_VALUE		0
+#define PP_HWID_10_GPIO_25_IS_GPIO		0
+
+/* GPIO 26: Unused */
+#define PP_HWID_10_GPIO_26_IS_OUTPUT		0
+#define PP_HWID_10_GPIO_26_IS_OPEN_DRAIN	0
+#define PP_HWID_10_GPIO_26_OUTPUT_VALUE		0
+#define PP_HWID_10_GPIO_26_IS_GPIO		0
+
+/* GPIO 27: Unused */
+#define PP_HWID_10_GPIO_27_IS_OUTPUT		0
+#define PP_HWID_10_GPIO_27_IS_OPEN_DRAIN	0
+#define PP_HWID_10_GPIO_27_OUTPUT_VALUE		0
+#define PP_HWID_10_GPIO_27_IS_GPIO		0
+
+/* GPIO 28: Unused */
+#define PP_HWID_10_GPIO_28_IS_OUTPUT		0
+#define PP_HWID_10_GPIO_28_IS_OPEN_DRAIN	0
+#define PP_HWID_10_GPIO_28_OUTPUT_VALUE		0
+#define PP_HWID_10_GPIO_28_IS_GPIO		0
+
+/* GPIO 29: Unused */
+#define PP_HWID_10_GPIO_29_IS_OUTPUT		0
+#define PP_HWID_10_GPIO_29_IS_OPEN_DRAIN	0
+#define PP_HWID_10_GPIO_29_OUTPUT_VALUE		0
+#define PP_HWID_10_GPIO_29_IS_GPIO		0
+
+/* GPIO 30: Unused */
+#define PP_HWID_10_GPIO_30_IS_OUTPUT		0
+#define PP_HWID_10_GPIO_30_IS_OPEN_DRAIN	0
+#define PP_HWID_10_GPIO_30_OUTPUT_VALUE		0
+#define PP_HWID_10_GPIO_30_IS_GPIO		0
+
+/* GPIO 31: Unused */
+#define PP_HWID_10_GPIO_31_IS_OUTPUT		0
+#define PP_HWID_10_GPIO_31_IS_OPEN_DRAIN	0
+#define PP_HWID_10_GPIO_31_OUTPUT_VALUE		0
+#define PP_HWID_10_GPIO_31_IS_GPIO		0
+
+/* ----------------------------------------------------------------------------
+ * External IRQ configuration
+ */
+
+/* USB_IRQ */
+#define PP_HWID_10_EXT_IRQ_00_HAS_POS_POLARITY	0
+#define PP_HWID_10_EXT_IRQ_00_IS_EDGE_TRIGGERED	0
+
+/* PHY_IRQ */
+#define PP_HWID_10_EXT_IRQ_01_HAS_POS_POLARITY	0
+#define PP_HWID_10_EXT_IRQ_01_IS_EDGE_TRIGGERED	0
+
+/* Unused */
+#define PP_HWID_10_EXT_IRQ_02_HAS_POS_POLARITY	0
+#define PP_HWID_10_EXT_IRQ_02_IS_EDGE_TRIGGERED	0
+
+/* Used as GPIO */
+#define PP_HWID_10_EXT_IRQ_03_HAS_POS_POLARITY	0
+#define PP_HWID_10_EXT_IRQ_03_IS_EDGE_TRIGGERED	0
+
+/* Unused */
+#define PP_HWID_10_EXT_IRQ_04_HAS_POS_POLARITY	0
+#define PP_HWID_10_EXT_IRQ_04_IS_EDGE_TRIGGERED	0
+
+/* VSC_IRQ */
+#define PP_HWID_10_EXT_IRQ_05_HAS_POS_POLARITY	0
+#define PP_HWID_10_EXT_IRQ_05_IS_EDGE_TRIGGERED	0
+
+/* Unused */
+#define PP_HWID_10_EXT_IRQ_06_HAS_POS_POLARITY	0
+#define PP_HWID_10_EXT_IRQ_06_IS_EDGE_TRIGGERED	0
+
+/* ----------------------------------------------------------------------------
+ * Chip Select configuration
+ */
+
+/* ---- Bank 0: Flash ---- */
+
+#define PP_HWID_10_CS_00_AP_BME		0x1	/* Burst mode enabled (1 bit) */
+#define PP_HWID_10_CS_00_AP_FWT		0x6	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_10_CS_00_AP_BWT		0x6	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_10_CS_00_AP_TWT		0x0	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_10_CS_00_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_10_CS_00_AP_OEN		0x1	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_10_CS_00_AP_WBN		0x1	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_10_CS_00_AP_WBF		0x1	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_10_CS_00_AP_TH		0x2	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_10_CS_00_AP_RE		0x0	/* Ready Enable (1 bit) */
+#define PP_HWID_10_CS_00_AP_SOR		0x1	/* Sample on Ready (1 bit) */
+#define PP_HWID_10_CS_00_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_10_CS_00_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_10_CS_00_CR_BAS		0xFF800000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_10_CS_00_CR_BS		0x3
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_10_CS_00_CR_BU		0x3
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_10_CS_00_CR_BW		0x1
+
+/* ---- Bank 1: USB ---- */
+
+/*
+ * NOTE: The USB chip has PerRW connected to its WR_N pin. This is wrong.
+ *       As a workaround we set the hold time to 0.
+ */
+
+#define PP_HWID_10_CS_01_AP_BME		0x0	/* Burst mode enabled (1 bit) */
+#define PP_HWID_10_CS_01_AP_FWT		0x0	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_10_CS_01_AP_BWT		0x0	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_10_CS_01_AP_TWT		0x5	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_10_CS_01_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_10_CS_01_AP_OEN		0x1	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_10_CS_01_AP_WBN		0x1	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_10_CS_01_AP_WBF		0x1	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_10_CS_01_AP_TH		0x0	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_10_CS_01_AP_RE		0x0	/* Ready Enable (1 bit) */
+#define PP_HWID_10_CS_01_AP_SOR		0x1	/* Sample on Ready (1 bit) */
+#define PP_HWID_10_CS_01_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_10_CS_01_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_10_CS_01_CR_BAS		0xF0000000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_10_CS_01_CR_BS		0x0
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_10_CS_01_CR_BU		0x3
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_10_CS_01_CR_BW		0x1
+
+/* ---- Bank 2: Hardware-ID ---- */
+
+#define PP_HWID_10_CS_02_AP_BME		0x0	/* Burst mode enabled (1 bit) */
+#define PP_HWID_10_CS_02_AP_FWT		0x0	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_10_CS_02_AP_BWT		0x0	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_10_CS_02_AP_TWT		0x8	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_10_CS_02_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_10_CS_02_AP_OEN		0x1	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_10_CS_02_AP_WBN		0x1	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_10_CS_02_AP_WBF		0x1	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_10_CS_02_AP_TH		0x2	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_10_CS_02_AP_RE		0x0	/* Ready Enable (1 bit) */
+#define PP_HWID_10_CS_02_AP_SOR		0x1	/* Sample on Ready (1 bit) */
+#define PP_HWID_10_CS_02_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_10_CS_02_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_10_CS_02_CR_BAS		0xF0600000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_10_CS_02_CR_BS		0x0
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_10_CS_02_CR_BU		0x3
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_10_CS_02_CR_BW		0x0
+
+
+/* ---- Bank 3: Unused ---- */
+
+#define PP_HWID_10_CS_03_AP_BME		0x0	/* Burst mode enabled (1 bit) */
+#define PP_HWID_10_CS_03_AP_FWT		0x0	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_10_CS_03_AP_BWT		0x0	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_10_CS_03_AP_TWT		0x0	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_10_CS_03_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_10_CS_03_AP_OEN		0x0	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_10_CS_03_AP_WBN		0x0	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_10_CS_03_AP_WBF		0x0	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_10_CS_03_AP_TH		0x0	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_10_CS_03_AP_RE		0x0	/* Ready Enable (1 bit) */
+#define PP_HWID_10_CS_03_AP_SOR		0x0	/* Sample on Ready (1 bit) */
+#define PP_HWID_10_CS_03_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_10_CS_03_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_10_CS_03_CR_BAS		0x00000000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_10_CS_03_CR_BS		0x0
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_10_CS_03_CR_BU		0x0
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_10_CS_03_CR_BW		0x0
+
+/* ---- Bank 4: VSC ---- */
+
+#define PP_HWID_10_CS_04_AP_BME		0x1	/* Burst mode enabled (1 bit) */
+#define PP_HWID_10_CS_04_AP_FWT		0x0	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_10_CS_04_AP_BWT		0x0	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_10_CS_04_AP_TWT		0x0	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_10_CS_04_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_10_CS_04_AP_OEN		0x0	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_10_CS_04_AP_WBN		0x0	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_10_CS_04_AP_WBF		0x0	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_10_CS_04_AP_TH		0x0	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_10_CS_04_AP_RE		0x1	/* Ready Enable (1 bit) */
+#define PP_HWID_10_CS_04_AP_SOR		0x1	/* Sample on Ready (1 bit) */
+#define PP_HWID_10_CS_04_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_10_CS_04_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_10_CS_04_CR_BAS		0xF1000000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_10_CS_04_CR_BS		0x3
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_10_CS_04_CR_BU		0x3
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_10_CS_04_CR_BW		0x1
+
+/* ---- Bank 5: Unused ---- */
+
+#define PP_HWID_10_CS_05_AP_BME		0x0	/* Burst mode enabled (1 bit) */
+#define PP_HWID_10_CS_05_AP_FWT		0x0	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_10_CS_05_AP_BWT		0x0	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_10_CS_05_AP_TWT		0x0	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_10_CS_05_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_10_CS_05_AP_OEN		0x0	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_10_CS_05_AP_WBN		0x0	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_10_CS_05_AP_WBF		0x0	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_10_CS_05_AP_TH		0x0	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_10_CS_05_AP_RE		0x0	/* Ready Enable (1 bit) */
+#define PP_HWID_10_CS_05_AP_SOR		0x0	/* Sample on Ready (1 bit) */
+#define PP_HWID_10_CS_05_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_10_CS_05_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_10_CS_05_CR_BAS		0x00000000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_10_CS_05_CR_BS		0x0
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_10_CS_05_CR_BU		0x0
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_10_CS_05_CR_BW		0x0
+
+/* ---- Bank 6: unused ---- */
+
+#define PP_HWID_10_CS_06_AP_BME		0x0	/* Burst mode enabled (1 bit) */
+#define PP_HWID_10_CS_06_AP_FWT		0x0	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_10_CS_06_AP_BWT		0x0	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_10_CS_06_AP_TWT		0x0	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_10_CS_06_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_10_CS_06_AP_OEN		0x0	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_10_CS_06_AP_WBN		0x0	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_10_CS_06_AP_WBF		0x0	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_10_CS_06_AP_TH		0x0	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_10_CS_06_AP_RE		0x0	/* Ready Enable (1 bit) */
+#define PP_HWID_10_CS_06_AP_SOR		0x0	/* Sample on Ready (1 bit) */
+#define PP_HWID_10_CS_06_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_10_CS_06_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_10_CS_06_CR_BAS		0x00000000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_10_CS_06_CR_BS		0x0
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_10_CS_06_CR_BU		0x0
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_10_CS_06_CR_BW		0x0
+
+/* ---- Bank 7: Unused ---- */
+
+#define PP_HWID_10_CS_07_AP_BME		0x0	/* Burst mode enabled (1 bit) */
+#define PP_HWID_10_CS_07_AP_FWT		0x0	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_10_CS_07_AP_BWT		0x0	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_10_CS_07_AP_TWT		0x0	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_10_CS_07_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_10_CS_07_AP_OEN		0x0	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_10_CS_07_AP_WBN		0x0	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_10_CS_07_AP_WBF		0x0	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_10_CS_07_AP_TH		0x0	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_10_CS_07_AP_RE		0x0	/* Ready Enable (1 bit) */
+#define PP_HWID_10_CS_07_AP_SOR		0x0	/* Sample on Ready (1 bit) */
+#define PP_HWID_10_CS_07_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_10_CS_07_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_10_CS_07_CR_BAS		0x00000000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_10_CS_07_CR_BS		0x0
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_10_CS_07_CR_BU		0x0
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_10_CS_07_CR_BW		0x0
+
+/* ----------------------------------------------------------------------------
+ * EBC configuration register
+ */
+
+#define PP_HWID_10_EBC_CFG_EBTC		0x1	/* ECB Three-State Control (1 bit) */
+#define PP_HWID_10_EBC_CFG_PTD		0x0	/* Device-Paced Time-out Disable (1 bit) */
+#define PP_HWID_10_EBC_CFG_RTC		0x3	/* Ready Timeout Count when PTD=0 (3 bit) */
+#define PP_HWID_10_EBC_CFG_EMPL		0x0	/* External Master Priority Low (2 bit) */
+#define PP_HWID_10_EBC_CFG_EMPH		0x0	/* External Master Priority High (2 bit) */
+#define PP_HWID_10_EBC_CFG_CSTC		0x1	/* Chip Select Three-State Control (1 bit) */
+#define PP_HWID_10_EBC_CFG_BPF		0x2	/* Burst Prefetch (2 bit) */
+#define PP_HWID_10_EBC_CFG_EMS		0x0	/* External Master Size (2 bit) */
+#define PP_HWID_10_EBC_CFG_PME		0x0	/* Power Management Enable (1 bit) */
+#define PP_HWID_10_EBC_CFG_PMT		0x0	/* Power Management Timer (5 bit) */
+
+#endif /* _HW_10_H */
Index: board/peppercon/hw_11.h
===================================================================
RCS file: board/peppercon/hw_11.h
diff -N board/peppercon/hw_11.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ board/peppercon/hw_11.h	29 Apr 2005 08:43:29 -0000	1.2
@@ -0,0 +1,520 @@
+/******************************************************************************
+ *
+ * Hardware configuration of AMD KIM-based board
+ *
+ * Hardware-ID: 0x11
+ *
+ */  
+
+#ifndef _HW_11_H
+#define _HW_11_H
+
+/* ----------------------------------------------------------------------------
+ * Miscellaneous Hardware Configuration
+ */
+
+#define PP_HWID_11_CPU_TYPE		PP_CPU_405EP	/* The CPU type */
+#define PP_HWID_11_FLASH_SIZE		(8*1024*1024)	/* Flash size in bytes */
+#define PP_HWID_11_SDRAM_ROWS		4096		/* SDRAM row count */
+#define PP_HWID_11_SDRAM_B0CR		0x00062001	/* 32MB @ 0x0 12x9x4 */
+#define PP_HWID_11_SDRAM_RTR		0x0618		/* 100 MHz; 64ms; 4k refresh */
+#define PP_HWID_11_SDRAM_TR		0x0086400D	/* 100 MHz; CASL=2, PTA=2, CTP=3, LDF=2, RFTA=7, RCD=2 */
+#define PP_HWID_11_SYS_CLK_FREQ		33333333	/* external frequency to PLL */
+#define PP_HWID_11_PHY_LED_CFG_VALUE	0x0472		/* LXT972A; register 0x14 */
+#define PP_HWID_11_BIGPHYSAREA_PAGES	1026		/* # of reserved pages for linux */
+#define PP_HWID_11_CONSOLE              PP_SERIAL_1
+
+#define PP_HWID_11_DESCRIPTION		"AMD KIM 1.2 / AMD MB"
+
+/* ----------------------------------------------------------------------------
+ * The PLL configuration (see PPC405EP manual section 7.2, 7.5.3 and 7.5.4)
+ */
+
+#define PP_HWID_11_DYNAMIC_PLL	   0
+
+/* ------------- 33 MHz SysClk Settings --------------- */
+/* Slow (66 MHz CPU-Clk) */
+#define PP_HWID_11_PLLMR0_SLOW (PLL_CPUDIV_2		\
+				   | PLL_PLBDIV_1	\
+				   | PLL_OPBDIV_2	\
+				   | PLL_EXTBUSDIV_2	\
+				   | PLL_MALDIV_1	\
+				   | PLL_PCIDIV_4)
+
+#define PP_HWID_11_PLLMR1_SLOW (PLL_FBKDIV_6		\
+				   | PLL_FWDDIVA_4	\
+				   | PLL_FWDDIVB_4	\
+				   | PLL_TUNE_15_M_40	\
+				   | PLL_TUNE_VCO_LOW)
+
+/* Fast (200 MHz CPU-Clk, 33 MHz bus) */
+#define PP_HWID_11_PLLMR0_FAST (PLL_CPUDIV_1		\
+				   | PLL_PLBDIV_2	\
+				   | PLL_OPBDIV_2	\
+				   | PLL_EXTBUSDIV_3	\
+				   | PLL_MALDIV_1	\
+				   | PLL_PCIDIV_3)
+
+#define PP_HWID_11_PLLMR1_FAST (PLL_FBKDIV_6		\
+				   | PLL_FWDDIVA_4	\
+				   | PLL_FWDDIVB_4	\
+				   | PLL_TUNE_15_M_40	\
+				   | PLL_TUNE_VCO_LOW)
+					
+#define PP_HWID_11_PLLMR0_DEFAULT	PP_HWID_11_PLLMR0_FAST
+#define PP_HWID_11_PLLMR1_DEFAULT	PP_HWID_11_PLLMR1_FAST
+
+/* ----------------------------------------------------------------------------
+ * GPIO configuration
+ */
+
+/* GPIO 0: Unused */
+#define PP_HWID_11_GPIO_00_IS_OUTPUT		0
+#define PP_HWID_11_GPIO_00_IS_OPEN_DRAIN	0
+#define PP_HWID_11_GPIO_00_OUTPUT_VALUE		0
+#define PP_HWID_11_GPIO_00_IS_GPIO		0
+
+/* GPIO 1: ATMEL_MISO */
+#define PP_HWID_11_GPIO_01_IS_OUTPUT		0
+#define PP_HWID_11_GPIO_01_IS_OPEN_DRAIN	0
+#define PP_HWID_11_GPIO_01_OUTPUT_VALUE		0
+#define PP_HWID_11_GPIO_01_IS_GPIO		1
+
+/* GPIO 2: ATMEL MOSI / FPGA_TDI */
+#define PP_HWID_11_GPIO_02_IS_OUTPUT		1
+#define PP_HWID_11_GPIO_02_IS_OPEN_DRAIN	0
+#define PP_HWID_11_GPIO_02_OUTPUT_VALUE		0
+#define PP_HWID_11_GPIO_02_IS_GPIO		1
+
+/* GPIO 3: ATMEL_RST */
+#define PP_HWID_11_GPIO_03_IS_OUTPUT		1
+#define PP_HWID_11_GPIO_03_IS_OPEN_DRAIN	0
+#define PP_HWID_11_GPIO_03_OUTPUT_VALUE		0
+#define PP_HWID_11_GPIO_03_IS_GPIO		1
+
+/* GPIO 4: ATMEL_SCK / FPGA_TCK */
+#define PP_HWID_11_GPIO_04_IS_OUTPUT		1
+#define PP_HWID_11_GPIO_04_IS_OPEN_DRAIN	0
+#define PP_HWID_11_GPIO_04_OUTPUT_VALUE		0
+#define PP_HWID_11_GPIO_04_IS_GPIO		1
+
+/* GPIO 5: Default Jumper */
+#define PP_HWID_11_GPIO_05_IS_OUTPUT		0
+#define PP_HWID_11_GPIO_05_IS_OPEN_DRAIN	0
+#define PP_HWID_11_GPIO_05_OUTPUT_VALUE		0
+#define PP_HWID_11_GPIO_05_IS_GPIO		1
+
+/* GPIO 6: Host RST */
+#define PP_HWID_11_GPIO_06_IS_OUTPUT		1
+#define PP_HWID_11_GPIO_06_IS_OPEN_DRAIN	0
+#define PP_HWID_11_GPIO_06_OUTPUT_VALUE		0
+#define PP_HWID_11_GPIO_06_IS_GPIO		1
+
+/* GPIO 7: Host ATX */
+#define PP_HWID_11_GPIO_07_IS_OUTPUT		1
+#define PP_HWID_11_GPIO_07_IS_OPEN_DRAIN	0
+#define PP_HWID_11_GPIO_07_OUTPUT_VALUE		0
+#define PP_HWID_11_GPIO_07_IS_GPIO		1
+
+/* GPIO 8: FPGA_TMS */
+#define PP_HWID_11_GPIO_08_IS_OUTPUT		1
+#define PP_HWID_11_GPIO_08_IS_OPEN_DRAIN	1
+#define PP_HWID_11_GPIO_08_OUTPUT_VALUE		1
+#define PP_HWID_11_GPIO_08_IS_GPIO		1
+
+/* GPIO 9: LED2 / Active low */
+#define PP_HWID_11_GPIO_09_IS_OUTPUT		1
+#define PP_HWID_11_GPIO_09_IS_OPEN_DRAIN	0
+#define PP_HWID_11_GPIO_09_OUTPUT_VALUE		0
+#define PP_HWID_11_GPIO_09_IS_GPIO		1
+
+/* GPIO 10: Unused */
+#define PP_HWID_11_GPIO_10_IS_OUTPUT		0
+#define PP_HWID_11_GPIO_10_IS_OPEN_DRAIN	0
+#define PP_HWID_11_GPIO_10_OUTPUT_VALUE		0
+#define PP_HWID_11_GPIO_10_IS_GPIO		0
+
+/* GPIO 11: Unused */
+#define PP_HWID_11_GPIO_11_IS_OUTPUT		0
+#define PP_HWID_11_GPIO_11_IS_OPEN_DRAIN	0
+#define PP_HWID_11_GPIO_11_OUTPUT_VALUE		0
+#define PP_HWID_11_GPIO_11_IS_GPIO		0
+
+/* GPIO 12: Unused */
+#define PP_HWID_11_GPIO_12_IS_OUTPUT		0
+#define PP_HWID_11_GPIO_12_IS_OPEN_DRAIN	0
+#define PP_HWID_11_GPIO_12_OUTPUT_VALUE		0
+#define PP_HWID_11_GPIO_12_IS_GPIO		0
+
+/* GPIO 13: Unused */
+#define PP_HWID_11_GPIO_13_IS_OUTPUT		0
+#define PP_HWID_11_GPIO_13_IS_OPEN_DRAIN	0
+#define PP_HWID_11_GPIO_13_OUTPUT_VALUE		0
+#define PP_HWID_11_GPIO_13_IS_GPIO		0
+
+/* GPIO 14: Unused */
+#define PP_HWID_11_GPIO_14_IS_OUTPUT		0
+#define PP_HWID_11_GPIO_14_IS_OPEN_DRAIN	0
+#define PP_HWID_11_GPIO_14_OUTPUT_VALUE		0
+#define PP_HWID_11_GPIO_14_IS_GPIO		0
+
+/* GPIO 15: Unused */
+#define PP_HWID_11_GPIO_15_IS_OUTPUT		0
+#define PP_HWID_11_GPIO_15_IS_OPEN_DRAIN	0
+#define PP_HWID_11_GPIO_15_OUTPUT_VALUE		0
+#define PP_HWID_11_GPIO_15_IS_GPIO		0
+
+/* GPIO 16: Unused */
+#define PP_HWID_11_GPIO_16_IS_OUTPUT		0
+#define PP_HWID_11_GPIO_16_IS_OPEN_DRAIN	0
+#define PP_HWID_11_GPIO_16_OUTPUT_VALUE		0
+#define PP_HWID_11_GPIO_16_IS_GPIO		0
+
+/* GPIO 17: Unused */
+#define PP_HWID_11_GPIO_17_IS_OUTPUT		0
+#define PP_HWID_11_GPIO_17_IS_OPEN_DRAIN	0
+#define PP_HWID_11_GPIO_17_OUTPUT_VALUE		0
+#define PP_HWID_11_GPIO_17_IS_GPIO		0
+
+/* GPIO 18: Unused */
+#define PP_HWID_11_GPIO_18_IS_OUTPUT		0
+#define PP_HWID_11_GPIO_18_IS_OPEN_DRAIN	0
+#define PP_HWID_11_GPIO_18_OUTPUT_VALUE		0
+#define PP_HWID_11_GPIO_18_IS_GPIO		0
+
+/* GPIO 19: Unused */
+#define PP_HWID_11_GPIO_19_IS_OUTPUT		0
+#define PP_HWID_11_GPIO_19_IS_OPEN_DRAIN	0
+#define PP_HWID_11_GPIO_19_OUTPUT_VALUE		0
+#define PP_HWID_11_GPIO_19_IS_GPIO		0
+
+/* GPIO 20: FPGA_TDO */
+#define PP_HWID_11_GPIO_20_IS_OUTPUT		0
+#define PP_HWID_11_GPIO_20_IS_OPEN_DRAIN	0
+#define PP_HWID_11_GPIO_20_OUTPUT_VALUE		0
+#define PP_HWID_11_GPIO_20_IS_GPIO		1
+
+/* GPIO 21: Unused */
+#define PP_HWID_11_GPIO_21_IS_OUTPUT		0
+#define PP_HWID_11_GPIO_21_IS_OPEN_DRAIN	0
+#define PP_HWID_11_GPIO_21_OUTPUT_VALUE		0
+#define PP_HWID_11_GPIO_21_IS_GPIO		0
+
+/* GPIO 22: Unused */
+#define PP_HWID_11_GPIO_22_IS_OUTPUT		0
+#define PP_HWID_11_GPIO_22_IS_OPEN_DRAIN	0
+#define PP_HWID_11_GPIO_22_OUTPUT_VALUE		0
+#define PP_HWID_11_GPIO_22_IS_GPIO		0
+
+/* GPIO 23: Unused */
+#define PP_HWID_11_GPIO_23_IS_OUTPUT		0
+#define PP_HWID_11_GPIO_23_IS_OPEN_DRAIN	0
+#define PP_HWID_11_GPIO_23_OUTPUT_VALUE		0
+#define PP_HWID_11_GPIO_23_IS_GPIO		0
+
+/* GPIO 24: Unused */
+#define PP_HWID_11_GPIO_24_IS_OUTPUT		0
+#define PP_HWID_11_GPIO_24_IS_OPEN_DRAIN	0
+#define PP_HWID_11_GPIO_24_OUTPUT_VALUE		0
+#define PP_HWID_11_GPIO_24_IS_GPIO		0
+
+/* GPIO 25: Unused */
+#define PP_HWID_11_GPIO_25_IS_OUTPUT		0
+#define PP_HWID_11_GPIO_25_IS_OPEN_DRAIN	0
+#define PP_HWID_11_GPIO_25_OUTPUT_VALUE		0
+#define PP_HWID_11_GPIO_25_IS_GPIO		0
+
+/* GPIO 26: Unused */
+#define PP_HWID_11_GPIO_26_IS_OUTPUT		0
+#define PP_HWID_11_GPIO_26_IS_OPEN_DRAIN	0
+#define PP_HWID_11_GPIO_26_OUTPUT_VALUE		0
+#define PP_HWID_11_GPIO_26_IS_GPIO		0
+
+/* GPIO 27: Unused */
+#define PP_HWID_11_GPIO_27_IS_OUTPUT		0
+#define PP_HWID_11_GPIO_27_IS_OPEN_DRAIN	0
+#define PP_HWID_11_GPIO_27_OUTPUT_VALUE		0
+#define PP_HWID_11_GPIO_27_IS_GPIO		0
+
+/* GPIO 28: Unused */
+#define PP_HWID_11_GPIO_28_IS_OUTPUT		0
+#define PP_HWID_11_GPIO_28_IS_OPEN_DRAIN	0
+#define PP_HWID_11_GPIO_28_OUTPUT_VALUE		0
+#define PP_HWID_11_GPIO_28_IS_GPIO		0
+
+/* GPIO 29: Unused */
+#define PP_HWID_11_GPIO_29_IS_OUTPUT		0
+#define PP_HWID_11_GPIO_29_IS_OPEN_DRAIN	0
+#define PP_HWID_11_GPIO_29_OUTPUT_VALUE		0
+#define PP_HWID_11_GPIO_29_IS_GPIO		0
+
+/* GPIO 30: Unused */
+#define PP_HWID_11_GPIO_30_IS_OUTPUT		0
+#define PP_HWID_11_GPIO_30_IS_OPEN_DRAIN	0
+#define PP_HWID_11_GPIO_30_OUTPUT_VALUE		0
+#define PP_HWID_11_GPIO_30_IS_GPIO		0
+
+/* GPIO 31: Unused */
+#define PP_HWID_11_GPIO_31_IS_OUTPUT		0
+#define PP_HWID_11_GPIO_31_IS_OPEN_DRAIN	0
+#define PP_HWID_11_GPIO_31_OUTPUT_VALUE		0
+#define PP_HWID_11_GPIO_31_IS_GPIO		0
+
+/* ----------------------------------------------------------------------------
+ * External IRQ configuration
+ */
+
+/* USB_IRQ */
+#define PP_HWID_11_EXT_IRQ_00_HAS_POS_POLARITY	0
+#define PP_HWID_11_EXT_IRQ_00_IS_EDGE_TRIGGERED	0
+
+/* PHY_IRQ */
+#define PP_HWID_11_EXT_IRQ_01_HAS_POS_POLARITY	0
+#define PP_HWID_11_EXT_IRQ_01_IS_EDGE_TRIGGERED	0
+
+/* Unused */
+#define PP_HWID_11_EXT_IRQ_02_HAS_POS_POLARITY	0
+#define PP_HWID_11_EXT_IRQ_02_IS_EDGE_TRIGGERED	0
+
+/* Used as GPIO */
+#define PP_HWID_11_EXT_IRQ_03_HAS_POS_POLARITY	0
+#define PP_HWID_11_EXT_IRQ_03_IS_EDGE_TRIGGERED	0
+
+/* Unused */
+#define PP_HWID_11_EXT_IRQ_04_HAS_POS_POLARITY	0
+#define PP_HWID_11_EXT_IRQ_04_IS_EDGE_TRIGGERED	0
+
+/* VSC_IRQ */
+#define PP_HWID_11_EXT_IRQ_05_HAS_POS_POLARITY	0
+#define PP_HWID_11_EXT_IRQ_05_IS_EDGE_TRIGGERED	0
+
+/* Unused */
+#define PP_HWID_11_EXT_IRQ_06_HAS_POS_POLARITY	0
+#define PP_HWID_11_EXT_IRQ_06_IS_EDGE_TRIGGERED	0
+
+/* ----------------------------------------------------------------------------
+ * Chip Select configuration
+ */
+
+/* ---- Bank 0: Flash ---- */
+
+#define PP_HWID_11_CS_00_AP_BME		0x1	/* Burst mode enabled (1 bit) */
+#define PP_HWID_11_CS_00_AP_FWT		0x6	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_11_CS_00_AP_BWT		0x6	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_11_CS_00_AP_TWT		0x0	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_11_CS_00_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_11_CS_00_AP_OEN		0x1	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_11_CS_00_AP_WBN		0x1	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_11_CS_00_AP_WBF		0x1	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_11_CS_00_AP_TH		0x2	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_11_CS_00_AP_RE		0x0	/* Ready Enable (1 bit) */
+#define PP_HWID_11_CS_00_AP_SOR		0x1	/* Sample on Ready (1 bit) */
+#define PP_HWID_11_CS_00_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_11_CS_00_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_11_CS_00_CR_BAS		0xFF800000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_11_CS_00_CR_BS		0x3
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_11_CS_00_CR_BU		0x3
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_11_CS_00_CR_BW		0x1
+
+/* ---- Bank 1: USB ---- */
+
+/*
+ * NOTE: The USB chip has PerRW connected to its WR_N pin. This is wrong.
+ *       As a workaround we set the hold time to 0.
+ */
+
+#define PP_HWID_11_CS_01_AP_BME		0x0	/* Burst mode enabled (1 bit) */
+#define PP_HWID_11_CS_01_AP_FWT		0x0	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_11_CS_01_AP_BWT		0x0	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_11_CS_01_AP_TWT		0x5	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_11_CS_01_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_11_CS_01_AP_OEN		0x1	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_11_CS_01_AP_WBN		0x1	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_11_CS_01_AP_WBF		0x1	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_11_CS_01_AP_TH		0x0	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_11_CS_01_AP_RE		0x0	/* Ready Enable (1 bit) */
+#define PP_HWID_11_CS_01_AP_SOR		0x1	/* Sample on Ready (1 bit) */
+#define PP_HWID_11_CS_01_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_11_CS_01_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_11_CS_01_CR_BAS		0xF0000000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_11_CS_01_CR_BS		0x0
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_11_CS_01_CR_BU		0x3
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_11_CS_01_CR_BW		0x1
+
+/* ---- Bank 2: Hardware-ID ---- */
+
+#define PP_HWID_11_CS_02_AP_BME		0x0	/* Burst mode enabled (1 bit) */
+#define PP_HWID_11_CS_02_AP_FWT		0x0	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_11_CS_02_AP_BWT		0x0	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_11_CS_02_AP_TWT		0x8	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_11_CS_02_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_11_CS_02_AP_OEN		0x1	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_11_CS_02_AP_WBN		0x1	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_11_CS_02_AP_WBF		0x1	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_11_CS_02_AP_TH		0x2	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_11_CS_02_AP_RE		0x0	/* Ready Enable (1 bit) */
+#define PP_HWID_11_CS_02_AP_SOR		0x1	/* Sample on Ready (1 bit) */
+#define PP_HWID_11_CS_02_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_11_CS_02_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_11_CS_02_CR_BAS		0xF0600000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_11_CS_02_CR_BS		0x0
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_11_CS_02_CR_BU		0x3
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_11_CS_02_CR_BW		0x0
+
+
+/* ---- Bank 3: Unused ---- */
+
+#define PP_HWID_11_CS_03_AP_BME		0x0	/* Burst mode enabled (1 bit) */
+#define PP_HWID_11_CS_03_AP_FWT		0x0	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_11_CS_03_AP_BWT		0x0	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_11_CS_03_AP_TWT		0x0	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_11_CS_03_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_11_CS_03_AP_OEN		0x0	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_11_CS_03_AP_WBN		0x0	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_11_CS_03_AP_WBF		0x0	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_11_CS_03_AP_TH		0x0	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_11_CS_03_AP_RE		0x0	/* Ready Enable (1 bit) */
+#define PP_HWID_11_CS_03_AP_SOR		0x0	/* Sample on Ready (1 bit) */
+#define PP_HWID_11_CS_03_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_11_CS_03_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_11_CS_03_CR_BAS		0x00000000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_11_CS_03_CR_BS		0x0
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_11_CS_03_CR_BU		0x0
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_11_CS_03_CR_BW		0x0
+
+/* ---- Bank 4: VSC ---- */
+
+#define PP_HWID_11_CS_04_AP_BME		0x1	/* Burst mode enabled (1 bit) */
+#define PP_HWID_11_CS_04_AP_FWT		0x0	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_11_CS_04_AP_BWT		0x0	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_11_CS_04_AP_TWT		0x0	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_11_CS_04_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_11_CS_04_AP_OEN		0x0	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_11_CS_04_AP_WBN		0x0	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_11_CS_04_AP_WBF		0x0	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_11_CS_04_AP_TH		0x0	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_11_CS_04_AP_RE		0x1	/* Ready Enable (1 bit) */
+#define PP_HWID_11_CS_04_AP_SOR		0x1	/* Sample on Ready (1 bit) */
+#define PP_HWID_11_CS_04_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_11_CS_04_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_11_CS_04_CR_BAS		0xF1000000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_11_CS_04_CR_BS		0x3
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_11_CS_04_CR_BU		0x3
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_11_CS_04_CR_BW		0x1
+
+/* ---- Bank 5: Unused ---- */
+
+#define PP_HWID_11_CS_05_AP_BME		0x0	/* Burst mode enabled (1 bit) */
+#define PP_HWID_11_CS_05_AP_FWT		0x0	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_11_CS_05_AP_BWT		0x0	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_11_CS_05_AP_TWT		0x0	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_11_CS_05_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_11_CS_05_AP_OEN		0x0	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_11_CS_05_AP_WBN		0x0	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_11_CS_05_AP_WBF		0x0	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_11_CS_05_AP_TH		0x0	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_11_CS_05_AP_RE		0x0	/* Ready Enable (1 bit) */
+#define PP_HWID_11_CS_05_AP_SOR		0x0	/* Sample on Ready (1 bit) */
+#define PP_HWID_11_CS_05_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_11_CS_05_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_11_CS_05_CR_BAS		0x00000000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_11_CS_05_CR_BS		0x0
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_11_CS_05_CR_BU		0x0
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_11_CS_05_CR_BW		0x0
+
+/* ---- Bank 6: unused ---- */
+
+#define PP_HWID_11_CS_06_AP_BME		0x0	/* Burst mode enabled (1 bit) */
+#define PP_HWID_11_CS_06_AP_FWT		0x0	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_11_CS_06_AP_BWT		0x0	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_11_CS_06_AP_TWT		0x0	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_11_CS_06_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_11_CS_06_AP_OEN		0x0	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_11_CS_06_AP_WBN		0x0	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_11_CS_06_AP_WBF		0x0	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_11_CS_06_AP_TH		0x0	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_11_CS_06_AP_RE		0x0	/* Ready Enable (1 bit) */
+#define PP_HWID_11_CS_06_AP_SOR		0x0	/* Sample on Ready (1 bit) */
+#define PP_HWID_11_CS_06_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_11_CS_06_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_11_CS_06_CR_BAS		0x00000000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_11_CS_06_CR_BS		0x0
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_11_CS_06_CR_BU		0x0
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_11_CS_06_CR_BW		0x0
+
+/* ---- Bank 7: Unused ---- */
+
+#define PP_HWID_11_CS_07_AP_BME		0x0	/* Burst mode enabled (1 bit) */
+#define PP_HWID_11_CS_07_AP_FWT		0x0	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_11_CS_07_AP_BWT		0x0	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_11_CS_07_AP_TWT		0x0	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_11_CS_07_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_11_CS_07_AP_OEN		0x0	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_11_CS_07_AP_WBN		0x0	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_11_CS_07_AP_WBF		0x0	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_11_CS_07_AP_TH		0x0	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_11_CS_07_AP_RE		0x0	/* Ready Enable (1 bit) */
+#define PP_HWID_11_CS_07_AP_SOR		0x0	/* Sample on Ready (1 bit) */
+#define PP_HWID_11_CS_07_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_11_CS_07_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_11_CS_07_CR_BAS		0x00000000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_11_CS_07_CR_BS		0x0
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_11_CS_07_CR_BU		0x0
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_11_CS_07_CR_BW		0x0
+
+/* ----------------------------------------------------------------------------
+ * EBC configuration register
+ */
+
+#define PP_HWID_11_EBC_CFG_EBTC		0x1	/* ECB Three-State Control (1 bit) */
+#define PP_HWID_11_EBC_CFG_PTD		0x0	/* Device-Paced Time-out Disable (1 bit) */
+#define PP_HWID_11_EBC_CFG_RTC		0x3	/* Ready Timeout Count when PTD=0 (3 bit) */
+#define PP_HWID_11_EBC_CFG_EMPL		0x0	/* External Master Priority Low (2 bit) */
+#define PP_HWID_11_EBC_CFG_EMPH		0x0	/* External Master Priority High (2 bit) */
+#define PP_HWID_11_EBC_CFG_CSTC		0x1	/* Chip Select Three-State Control (1 bit) */
+#define PP_HWID_11_EBC_CFG_BPF		0x2	/* Burst Prefetch (2 bit) */
+#define PP_HWID_11_EBC_CFG_EMS		0x0	/* External Master Size (2 bit) */
+#define PP_HWID_11_EBC_CFG_PME		0x0	/* Power Management Enable (1 bit) */
+#define PP_HWID_11_EBC_CFG_PMT		0x0	/* Power Management Timer (5 bit) */
+
+#endif /* _HW_11_H */
Index: board/peppercon/hw_12.h
===================================================================
RCS file: board/peppercon/hw_12.h
diff -N board/peppercon/hw_12.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ board/peppercon/hw_12.h	29 Apr 2005 08:43:29 -0000	1.1
@@ -0,0 +1,520 @@
+/******************************************************************************
+ *
+ * Hardware configuration of KIM 2.0 / MB "B52" / FPGA C12
+ *
+ * Hardware-ID: 0x12
+ *
+ */  
+
+#ifndef _HW_12_H
+#define _HW_12_H
+
+/* ----------------------------------------------------------------------------
+ * Miscellaneous Hardware Configuration
+ */
+
+#define PP_HWID_12_CPU_TYPE		PP_CPU_405EP	/* The CPU type */
+#define PP_HWID_12_FLASH_SIZE		(8*1024*1024)	/* Flash size in bytes */
+#define PP_HWID_12_SDRAM_ROWS		4096		/* SDRAM row count */
+#define PP_HWID_12_SDRAM_B0CR		0x00062001	/* 32MB @ 0x0 12x9x4 */
+#define PP_HWID_12_SDRAM_RTR		0x0618		/* 100 MHz; 64ms; 4k refresh */
+#define PP_HWID_12_SDRAM_TR		0x0086400D	/* 100 MHz; CASL=2, PTA=2, CTP=3, LDF=2, RFTA=7, RCD=2 */
+#define PP_HWID_12_SYS_CLK_FREQ		33333333	/* external frequency to PLL */
+#define PP_HWID_12_PHY_LED_CFG_VALUE	0x0472		/* LXT972A; register 0x14 */
+#define PP_HWID_12_BIGPHYSAREA_PAGES	1026		/* # of reserved pages for linux */
+#define PP_HWID_12_CONSOLE              PP_SERIAL_0
+
+#define PP_HWID_12_DESCRIPTION		"KIM 2.0 / FPGA C12"
+
+/* ----------------------------------------------------------------------------
+ * The PLL configuration (see PPC405EP manual section 7.2, 7.5.3 and 7.5.4)
+ */
+
+#define PP_HWID_12_DYNAMIC_PLL	   0
+
+/* ------------- 33 MHz SysClk Settings --------------- */
+/* Slow (66 MHz CPU-Clk) */
+#define PP_HWID_12_PLLMR0_SLOW (PLL_CPUDIV_2		\
+				   | PLL_PLBDIV_1	\
+				   | PLL_OPBDIV_2	\
+				   | PLL_EXTBUSDIV_2	\
+				   | PLL_MALDIV_1	\
+				   | PLL_PCIDIV_4)
+
+#define PP_HWID_12_PLLMR1_SLOW (PLL_FBKDIV_6		\
+				   | PLL_FWDDIVA_4	\
+				   | PLL_FWDDIVB_4	\
+				   | PLL_TUNE_15_M_40	\
+				   | PLL_TUNE_VCO_LOW)
+
+/* Fast (200 MHz CPU-Clk, 50 MHz bus) */
+#define PP_HWID_12_PLLMR0_FAST (PLL_CPUDIV_1		\
+				   | PLL_PLBDIV_2	\
+				   | PLL_OPBDIV_2	\
+				   | PLL_EXTBUSDIV_2	\
+				   | PLL_MALDIV_1	\
+				   | PLL_PCIDIV_3)
+
+#define PP_HWID_12_PLLMR1_FAST (PLL_FBKDIV_6		\
+				   | PLL_FWDDIVA_4	\
+				   | PLL_FWDDIVB_4	\
+				   | PLL_TUNE_15_M_40	\
+				   | PLL_TUNE_VCO_LOW)
+					
+#define PP_HWID_12_PLLMR0_DEFAULT	PP_HWID_12_PLLMR0_FAST
+#define PP_HWID_12_PLLMR1_DEFAULT	PP_HWID_12_PLLMR1_FAST
+
+/* ----------------------------------------------------------------------------
+ * GPIO configuration
+ */
+
+/* GPIO 0: Unused */
+#define PP_HWID_12_GPIO_00_IS_OUTPUT		0
+#define PP_HWID_12_GPIO_00_IS_OPEN_DRAIN	0
+#define PP_HWID_12_GPIO_00_OUTPUT_VALUE		0
+#define PP_HWID_12_GPIO_00_IS_GPIO		0
+
+/* GPIO 1: ATMEL_MISO */
+#define PP_HWID_12_GPIO_01_IS_OUTPUT		0
+#define PP_HWID_12_GPIO_01_IS_OPEN_DRAIN	0
+#define PP_HWID_12_GPIO_01_OUTPUT_VALUE		0
+#define PP_HWID_12_GPIO_01_IS_GPIO		1
+
+/* GPIO 2: ATMEL MOSI / FPGA_TDI */
+#define PP_HWID_12_GPIO_02_IS_OUTPUT		1
+#define PP_HWID_12_GPIO_02_IS_OPEN_DRAIN	0
+#define PP_HWID_12_GPIO_02_OUTPUT_VALUE		0
+#define PP_HWID_12_GPIO_02_IS_GPIO		1
+
+/* GPIO 3: ATMEL_RST */
+#define PP_HWID_12_GPIO_03_IS_OUTPUT		1
+#define PP_HWID_12_GPIO_03_IS_OPEN_DRAIN	0
+#define PP_HWID_12_GPIO_03_OUTPUT_VALUE		0
+#define PP_HWID_12_GPIO_03_IS_GPIO		1
+
+/* GPIO 4: ATMEL_SCK / FPGA_TCK */
+#define PP_HWID_12_GPIO_04_IS_OUTPUT		1
+#define PP_HWID_12_GPIO_04_IS_OPEN_DRAIN	0
+#define PP_HWID_12_GPIO_04_OUTPUT_VALUE		0
+#define PP_HWID_12_GPIO_04_IS_GPIO		1
+
+/* GPIO 5: Default Jumper */
+#define PP_HWID_12_GPIO_05_IS_OUTPUT		0
+#define PP_HWID_12_GPIO_05_IS_OPEN_DRAIN	0
+#define PP_HWID_12_GPIO_05_OUTPUT_VALUE		0
+#define PP_HWID_12_GPIO_05_IS_GPIO		1
+
+/* GPIO 6: Host RST */
+#define PP_HWID_12_GPIO_06_IS_OUTPUT		1
+#define PP_HWID_12_GPIO_06_IS_OPEN_DRAIN	0
+#define PP_HWID_12_GPIO_06_OUTPUT_VALUE		0
+#define PP_HWID_12_GPIO_06_IS_GPIO		1
+
+/* GPIO 7: Host ATX */
+#define PP_HWID_12_GPIO_07_IS_OUTPUT		1
+#define PP_HWID_12_GPIO_07_IS_OPEN_DRAIN	0
+#define PP_HWID_12_GPIO_07_OUTPUT_VALUE		0
+#define PP_HWID_12_GPIO_07_IS_GPIO		1
+
+/* GPIO 8: FPGA_TMS */
+#define PP_HWID_12_GPIO_08_IS_OUTPUT		1
+#define PP_HWID_12_GPIO_08_IS_OPEN_DRAIN	1
+#define PP_HWID_12_GPIO_08_OUTPUT_VALUE		1
+#define PP_HWID_12_GPIO_08_IS_GPIO		1
+
+/* GPIO 9: LED2 / Active low */
+#define PP_HWID_12_GPIO_09_IS_OUTPUT		1
+#define PP_HWID_12_GPIO_09_IS_OPEN_DRAIN	0
+#define PP_HWID_12_GPIO_09_OUTPUT_VALUE		0
+#define PP_HWID_12_GPIO_09_IS_GPIO		1
+
+/* GPIO 10: Unused */
+#define PP_HWID_12_GPIO_10_IS_OUTPUT		0
+#define PP_HWID_12_GPIO_10_IS_OPEN_DRAIN	0
+#define PP_HWID_12_GPIO_10_OUTPUT_VALUE		0
+#define PP_HWID_12_GPIO_10_IS_GPIO		0
+
+/* GPIO 11: Unused */
+#define PP_HWID_12_GPIO_11_IS_OUTPUT		0
+#define PP_HWID_12_GPIO_11_IS_OPEN_DRAIN	0
+#define PP_HWID_12_GPIO_11_OUTPUT_VALUE		0
+#define PP_HWID_12_GPIO_11_IS_GPIO		0
+
+/* GPIO 12: Unused */
+#define PP_HWID_12_GPIO_12_IS_OUTPUT		0
+#define PP_HWID_12_GPIO_12_IS_OPEN_DRAIN	0
+#define PP_HWID_12_GPIO_12_OUTPUT_VALUE		0
+#define PP_HWID_12_GPIO_12_IS_GPIO		0
+
+/* GPIO 13: Unused */
+#define PP_HWID_12_GPIO_13_IS_OUTPUT		0
+#define PP_HWID_12_GPIO_13_IS_OPEN_DRAIN	0
+#define PP_HWID_12_GPIO_13_OUTPUT_VALUE		0
+#define PP_HWID_12_GPIO_13_IS_GPIO		0
+
+/* GPIO 14: Unused */
+#define PP_HWID_12_GPIO_14_IS_OUTPUT		0
+#define PP_HWID_12_GPIO_14_IS_OPEN_DRAIN	0
+#define PP_HWID_12_GPIO_14_OUTPUT_VALUE		0
+#define PP_HWID_12_GPIO_14_IS_GPIO		0
+
+/* GPIO 15: Unused */
+#define PP_HWID_12_GPIO_15_IS_OUTPUT		0
+#define PP_HWID_12_GPIO_15_IS_OPEN_DRAIN	0
+#define PP_HWID_12_GPIO_15_OUTPUT_VALUE		0
+#define PP_HWID_12_GPIO_15_IS_GPIO		0
+
+/* GPIO 16: Unused */
+#define PP_HWID_12_GPIO_16_IS_OUTPUT		0
+#define PP_HWID_12_GPIO_16_IS_OPEN_DRAIN	0
+#define PP_HWID_12_GPIO_16_OUTPUT_VALUE		0
+#define PP_HWID_12_GPIO_16_IS_GPIO		0
+
+/* GPIO 17: Unused */
+#define PP_HWID_12_GPIO_17_IS_OUTPUT		0
+#define PP_HWID_12_GPIO_17_IS_OPEN_DRAIN	0
+#define PP_HWID_12_GPIO_17_OUTPUT_VALUE		0
+#define PP_HWID_12_GPIO_17_IS_GPIO		0
+
+/* GPIO 18: Unused */
+#define PP_HWID_12_GPIO_18_IS_OUTPUT		0
+#define PP_HWID_12_GPIO_18_IS_OPEN_DRAIN	0
+#define PP_HWID_12_GPIO_18_OUTPUT_VALUE		0
+#define PP_HWID_12_GPIO_18_IS_GPIO		0
+
+/* GPIO 19: Unused */
+#define PP_HWID_12_GPIO_19_IS_OUTPUT		0
+#define PP_HWID_12_GPIO_19_IS_OPEN_DRAIN	0
+#define PP_HWID_12_GPIO_19_OUTPUT_VALUE		0
+#define PP_HWID_12_GPIO_19_IS_GPIO		0
+
+/* GPIO 20: FPGA_TDO */
+#define PP_HWID_12_GPIO_20_IS_OUTPUT		0
+#define PP_HWID_12_GPIO_20_IS_OPEN_DRAIN	0
+#define PP_HWID_12_GPIO_20_OUTPUT_VALUE		0
+#define PP_HWID_12_GPIO_20_IS_GPIO		1
+
+/* GPIO 21: Unused */
+#define PP_HWID_12_GPIO_21_IS_OUTPUT		0
+#define PP_HWID_12_GPIO_21_IS_OPEN_DRAIN	0
+#define PP_HWID_12_GPIO_21_OUTPUT_VALUE		0
+#define PP_HWID_12_GPIO_21_IS_GPIO		0
+
+/* GPIO 22: Unused */
+#define PP_HWID_12_GPIO_22_IS_OUTPUT		0
+#define PP_HWID_12_GPIO_22_IS_OPEN_DRAIN	0
+#define PP_HWID_12_GPIO_22_OUTPUT_VALUE		0
+#define PP_HWID_12_GPIO_22_IS_GPIO		0
+
+/* GPIO 23: Unused */
+#define PP_HWID_12_GPIO_23_IS_OUTPUT		0
+#define PP_HWID_12_GPIO_23_IS_OPEN_DRAIN	0
+#define PP_HWID_12_GPIO_23_OUTPUT_VALUE		0
+#define PP_HWID_12_GPIO_23_IS_GPIO		0
+
+/* GPIO 24: Unused */
+#define PP_HWID_12_GPIO_24_IS_OUTPUT		0
+#define PP_HWID_12_GPIO_24_IS_OPEN_DRAIN	0
+#define PP_HWID_12_GPIO_24_OUTPUT_VALUE		0
+#define PP_HWID_12_GPIO_24_IS_GPIO		0
+
+/* GPIO 25: Unused */
+#define PP_HWID_12_GPIO_25_IS_OUTPUT		0
+#define PP_HWID_12_GPIO_25_IS_OPEN_DRAIN	0
+#define PP_HWID_12_GPIO_25_OUTPUT_VALUE		0
+#define PP_HWID_12_GPIO_25_IS_GPIO		0
+
+/* GPIO 26: Unused */
+#define PP_HWID_12_GPIO_26_IS_OUTPUT		0
+#define PP_HWID_12_GPIO_26_IS_OPEN_DRAIN	0
+#define PP_HWID_12_GPIO_26_OUTPUT_VALUE		0
+#define PP_HWID_12_GPIO_26_IS_GPIO		0
+
+/* GPIO 27: Unused */
+#define PP_HWID_12_GPIO_27_IS_OUTPUT		0
+#define PP_HWID_12_GPIO_27_IS_OPEN_DRAIN	0
+#define PP_HWID_12_GPIO_27_OUTPUT_VALUE		0
+#define PP_HWID_12_GPIO_27_IS_GPIO		0
+
+/* GPIO 28: Unused */
+#define PP_HWID_12_GPIO_28_IS_OUTPUT		0
+#define PP_HWID_12_GPIO_28_IS_OPEN_DRAIN	0
+#define PP_HWID_12_GPIO_28_OUTPUT_VALUE		0
+#define PP_HWID_12_GPIO_28_IS_GPIO		0
+
+/* GPIO 29: Unused */
+#define PP_HWID_12_GPIO_29_IS_OUTPUT		0
+#define PP_HWID_12_GPIO_29_IS_OPEN_DRAIN	0
+#define PP_HWID_12_GPIO_29_OUTPUT_VALUE		0
+#define PP_HWID_12_GPIO_29_IS_GPIO		0
+
+/* GPIO 30: Unused */
+#define PP_HWID_12_GPIO_30_IS_OUTPUT		0
+#define PP_HWID_12_GPIO_30_IS_OPEN_DRAIN	0
+#define PP_HWID_12_GPIO_30_OUTPUT_VALUE		0
+#define PP_HWID_12_GPIO_30_IS_GPIO		0
+
+/* GPIO 31: Unused */
+#define PP_HWID_12_GPIO_31_IS_OUTPUT		0
+#define PP_HWID_12_GPIO_31_IS_OPEN_DRAIN	0
+#define PP_HWID_12_GPIO_31_OUTPUT_VALUE		0
+#define PP_HWID_12_GPIO_31_IS_GPIO		0
+
+/* ----------------------------------------------------------------------------
+ * External IRQ configuration
+ */
+
+/* USB_IRQ */
+#define PP_HWID_12_EXT_IRQ_00_HAS_POS_POLARITY	0
+#define PP_HWID_12_EXT_IRQ_00_IS_EDGE_TRIGGERED	0
+
+/* PHY_IRQ */
+#define PP_HWID_12_EXT_IRQ_01_HAS_POS_POLARITY	0
+#define PP_HWID_12_EXT_IRQ_01_IS_EDGE_TRIGGERED	0
+
+/* Unused */
+#define PP_HWID_12_EXT_IRQ_02_HAS_POS_POLARITY	0
+#define PP_HWID_12_EXT_IRQ_02_IS_EDGE_TRIGGERED	0
+
+/* Used as GPIO */
+#define PP_HWID_12_EXT_IRQ_03_HAS_POS_POLARITY	0
+#define PP_HWID_12_EXT_IRQ_03_IS_EDGE_TRIGGERED	0
+
+/* Unused */
+#define PP_HWID_12_EXT_IRQ_04_HAS_POS_POLARITY	0
+#define PP_HWID_12_EXT_IRQ_04_IS_EDGE_TRIGGERED	0
+
+/* VSC_IRQ */
+#define PP_HWID_12_EXT_IRQ_05_HAS_POS_POLARITY	0
+#define PP_HWID_12_EXT_IRQ_05_IS_EDGE_TRIGGERED	0
+
+/* Unused */
+#define PP_HWID_12_EXT_IRQ_06_HAS_POS_POLARITY	0
+#define PP_HWID_12_EXT_IRQ_06_IS_EDGE_TRIGGERED	0
+
+/* ----------------------------------------------------------------------------
+ * Chip Select configuration
+ */
+
+/* ---- Bank 0: Flash ---- */
+
+#define PP_HWID_12_CS_00_AP_BME		0x1	/* Burst mode enabled (1 bit) */
+#define PP_HWID_12_CS_00_AP_FWT		0x6	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_12_CS_00_AP_BWT		0x6	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_12_CS_00_AP_TWT		0x0	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_12_CS_00_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_12_CS_00_AP_OEN		0x1	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_12_CS_00_AP_WBN		0x1	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_12_CS_00_AP_WBF		0x1	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_12_CS_00_AP_TH		0x2	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_12_CS_00_AP_RE		0x0	/* Ready Enable (1 bit) */
+#define PP_HWID_12_CS_00_AP_SOR		0x1	/* Sample on Ready (1 bit) */
+#define PP_HWID_12_CS_00_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_12_CS_00_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_12_CS_00_CR_BAS		0xFF800000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_12_CS_00_CR_BS		0x3
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_12_CS_00_CR_BU		0x3
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_12_CS_00_CR_BW		0x1
+
+/* ---- Bank 1: USB ---- */
+
+/*
+ * NOTE: The USB chip has PerRW connected to its WR_N pin. This is wrong.
+ *       As a workaround we set the hold time to 0.
+ */
+
+#define PP_HWID_12_CS_01_AP_BME		0x0	/* Burst mode enabled (1 bit) */
+#define PP_HWID_12_CS_01_AP_FWT		0x0	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_12_CS_01_AP_BWT		0x0	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_12_CS_01_AP_TWT		0x5	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_12_CS_01_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_12_CS_01_AP_OEN		0x1	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_12_CS_01_AP_WBN		0x1	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_12_CS_01_AP_WBF		0x1	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_12_CS_01_AP_TH		0x0	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_12_CS_01_AP_RE		0x0	/* Ready Enable (1 bit) */
+#define PP_HWID_12_CS_01_AP_SOR		0x1	/* Sample on Ready (1 bit) */
+#define PP_HWID_12_CS_01_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_12_CS_01_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_12_CS_01_CR_BAS		0xF0000000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_12_CS_01_CR_BS		0x0
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_12_CS_01_CR_BU		0x3
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_12_CS_01_CR_BW		0x1
+
+/* ---- Bank 2: Hardware-ID ---- */
+
+#define PP_HWID_12_CS_02_AP_BME		0x0	/* Burst mode enabled (1 bit) */
+#define PP_HWID_12_CS_02_AP_FWT		0x0	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_12_CS_02_AP_BWT		0x0	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_12_CS_02_AP_TWT		0x8	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_12_CS_02_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_12_CS_02_AP_OEN		0x1	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_12_CS_02_AP_WBN		0x1	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_12_CS_02_AP_WBF		0x1	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_12_CS_02_AP_TH		0x2	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_12_CS_02_AP_RE		0x0	/* Ready Enable (1 bit) */
+#define PP_HWID_12_CS_02_AP_SOR		0x1	/* Sample on Ready (1 bit) */
+#define PP_HWID_12_CS_02_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_12_CS_02_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_12_CS_02_CR_BAS		0xF0600000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_12_CS_02_CR_BS		0x0
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_12_CS_02_CR_BU		0x3
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_12_CS_02_CR_BW		0x0
+
+
+/* ---- Bank 3: Unused ---- */
+
+#define PP_HWID_12_CS_03_AP_BME		0x0	/* Burst mode enabled (1 bit) */
+#define PP_HWID_12_CS_03_AP_FWT		0x0	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_12_CS_03_AP_BWT		0x0	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_12_CS_03_AP_TWT		0x0	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_12_CS_03_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_12_CS_03_AP_OEN		0x0	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_12_CS_03_AP_WBN		0x0	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_12_CS_03_AP_WBF		0x0	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_12_CS_03_AP_TH		0x0	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_12_CS_03_AP_RE		0x0	/* Ready Enable (1 bit) */
+#define PP_HWID_12_CS_03_AP_SOR		0x0	/* Sample on Ready (1 bit) */
+#define PP_HWID_12_CS_03_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_12_CS_03_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_12_CS_03_CR_BAS		0x00000000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_12_CS_03_CR_BS		0x0
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_12_CS_03_CR_BU		0x0
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_12_CS_03_CR_BW		0x0
+
+/* ---- Bank 4: VSC ---- */
+
+#define PP_HWID_12_CS_04_AP_BME		0x1	/* Burst mode enabled (1 bit) */
+#define PP_HWID_12_CS_04_AP_FWT		0x0	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_12_CS_04_AP_BWT		0x0	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_12_CS_04_AP_TWT		0x0	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_12_CS_04_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_12_CS_04_AP_OEN		0x0	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_12_CS_04_AP_WBN		0x0	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_12_CS_04_AP_WBF		0x0	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_12_CS_04_AP_TH		0x0	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_12_CS_04_AP_RE		0x1	/* Ready Enable (1 bit) */
+#define PP_HWID_12_CS_04_AP_SOR		0x1	/* Sample on Ready (1 bit) */
+#define PP_HWID_12_CS_04_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_12_CS_04_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_12_CS_04_CR_BAS		0xF1000000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_12_CS_04_CR_BS		0x3
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_12_CS_04_CR_BU		0x3
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_12_CS_04_CR_BW		0x1
+
+/* ---- Bank 5: Unused ---- */
+
+#define PP_HWID_12_CS_05_AP_BME		0x0	/* Burst mode enabled (1 bit) */
+#define PP_HWID_12_CS_05_AP_FWT		0x0	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_12_CS_05_AP_BWT		0x0	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_12_CS_05_AP_TWT		0x0	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_12_CS_05_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_12_CS_05_AP_OEN		0x0	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_12_CS_05_AP_WBN		0x0	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_12_CS_05_AP_WBF		0x0	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_12_CS_05_AP_TH		0x0	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_12_CS_05_AP_RE		0x0	/* Ready Enable (1 bit) */
+#define PP_HWID_12_CS_05_AP_SOR		0x0	/* Sample on Ready (1 bit) */
+#define PP_HWID_12_CS_05_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_12_CS_05_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_12_CS_05_CR_BAS		0x00000000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_12_CS_05_CR_BS		0x0
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_12_CS_05_CR_BU		0x0
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_12_CS_05_CR_BW		0x0
+
+/* ---- Bank 6: unused ---- */
+
+#define PP_HWID_12_CS_06_AP_BME		0x0	/* Burst mode enabled (1 bit) */
+#define PP_HWID_12_CS_06_AP_FWT		0x0	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_12_CS_06_AP_BWT		0x0	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_12_CS_06_AP_TWT		0x0	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_12_CS_06_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_12_CS_06_AP_OEN		0x0	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_12_CS_06_AP_WBN		0x0	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_12_CS_06_AP_WBF		0x0	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_12_CS_06_AP_TH		0x0	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_12_CS_06_AP_RE		0x0	/* Ready Enable (1 bit) */
+#define PP_HWID_12_CS_06_AP_SOR		0x0	/* Sample on Ready (1 bit) */
+#define PP_HWID_12_CS_06_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_12_CS_06_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_12_CS_06_CR_BAS		0x00000000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_12_CS_06_CR_BS		0x0
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_12_CS_06_CR_BU		0x0
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_12_CS_06_CR_BW		0x0
+
+/* ---- Bank 7: Unused ---- */
+
+#define PP_HWID_12_CS_07_AP_BME		0x0	/* Burst mode enabled (1 bit) */
+#define PP_HWID_12_CS_07_AP_FWT		0x0	/* First Wait for Burst mode (5 bit) */
+#define PP_HWID_12_CS_07_AP_BWT		0x0	/* Non-first Wait for Burst mode (3 bit) */
+#define PP_HWID_12_CS_07_AP_TWT		0x0	/* Transfer Wait for non Burst mode (8 bit) */
+#define PP_HWID_12_CS_07_AP_CSN		0x0	/* /PerCS on after address delay (2 bit) */
+#define PP_HWID_12_CS_07_AP_OEN		0x0	/* /PerOE on after /PerCS delay (2 bit) */
+#define PP_HWID_12_CS_07_AP_WBN		0x0	/* /PerWBE0:3 on after /PerCS if BEM = 0 (2 bit) */
+#define PP_HWID_12_CS_07_AP_WBF		0x0	/* /PerWBE0:3 off before /PerCS off if BEM = 0 (2 bit) */
+#define PP_HWID_12_CS_07_AP_TH		0x0	/* Transfer hold after end of transfer (3 bit) */
+#define PP_HWID_12_CS_07_AP_RE		0x0	/* Ready Enable (1 bit) */
+#define PP_HWID_12_CS_07_AP_SOR		0x0	/* Sample on Ready (1 bit) */
+#define PP_HWID_12_CS_07_AP_BEM		0x0	/* Byte Enable Mode (1 bit) */
+#define PP_HWID_12_CS_07_AP_PEN		0x0	/* Partity Enable (1 bit) */
+
+/* Base Address - must be multiple of BS */
+#define PP_HWID_12_CS_07_CR_BAS		0x00000000
+/* Bank Size (3 bit); 0b000 = 1MB, 0b001 = 2MB, ..., 0b111 = 128MB */
+#define PP_HWID_12_CS_07_CR_BS		0x0
+/* Bank Usage (2 bit); 0x0 = disabled; 0x1 = r/o; 0x2 = w/o; 0x3 = r/w */
+#define PP_HWID_12_CS_07_CR_BU		0x0
+/* BusWidth (2 bit); 0x0 = 8bit; 0x1 = 16bit; 0x2 = 32bit; 0x3 = reserved */
+#define PP_HWID_12_CS_07_CR_BW		0x0
+
+/* ----------------------------------------------------------------------------
+ * EBC configuration register
+ */
+
+#define PP_HWID_12_EBC_CFG_EBTC		0x1	/* ECB Three-State Control (1 bit) */
+#define PP_HWID_12_EBC_CFG_PTD		0x0	/* Device-Paced Time-out Disable (1 bit) */
+#define PP_HWID_12_EBC_CFG_RTC		0x3	/* Ready Timeout Count when PTD=0 (3 bit) */
+#define PP_HWID_12_EBC_CFG_EMPL		0x0	/* External Master Priority Low (2 bit) */
+#define PP_HWID_12_EBC_CFG_EMPH		0x0	/* External Master Priority High (2 bit) */
+#define PP_HWID_12_EBC_CFG_CSTC		0x1	/* Chip Select Three-State Control (1 bit) */
+#define PP_HWID_12_EBC_CFG_BPF		0x2	/* Burst Prefetch (2 bit) */
+#define PP_HWID_12_EBC_CFG_EMS		0x0	/* External Master Size (2 bit) */
+#define PP_HWID_12_EBC_CFG_PME		0x0	/* Power Management Enable (1 bit) */
+#define PP_HWID_12_EBC_CFG_PMT		0x0	/* Power Management Timer (5 bit) */
+
+#endif /* _HW_12_H */
Index: board/peppercon/init.S
===================================================================
RCS file: board/peppercon/init.S
diff -N board/peppercon/init.S
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ board/peppercon/init.S	3 Feb 2005 10:35:41 -0000	1.1
@@ -0,0 +1,168 @@
+/* ------------------------------------------------------------------------- */
+/*       This source code has been made available to you by IBM on an AS-IS  */
+/*       basis.  Anyone receiving this source is licensed under IBM          */
+/*       copyrights to use it in any way he or she deems fit, including      */
+/*       copying it, modifying it, compiling it, and redistributing it either*/
+/*       with or without modifications.  No license under IBM patents or     */
+/*       patent applications is to be implied by the copyright license.      */
+/*                                                                           */
+/*       Any user of this software should understand that IBM cannot provide */
+/*       technical support for this software and will not be responsible for */
+/*       any consequences resulting from the use of this software.           */
+/*                                                                           */
+/*       Any person who transfers this source code or any derivative work    */
+/*       must include the IBM copyright notice, this paragraph, and the      */
+/*       preceding two paragraphs in the transferred software.               */
+/*                                                                           */
+/*       COPYRIGHT   I B M   CORPORATION 1995                                */
+/*       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M                     */
+/* ------------------------------------------------------------------------- */
+
+/* ------------------------------------------------------------------------- */
+/* Function:     ext_bus_cntlr_init					     */
+/* Description:  Initializes the External Bus Controller for the external    */
+/*		peripherals. IMPORTANT: For pass1 this code must run from    */
+/*		cache since you can not reliably change a peripheral banks   */
+/*		timing register (pbxap) while running code from that bank.   */
+/*		For ex., since we are running from ROM on bank 0, we can NOT */
+/*		execute the code that modifies bank 0 timings from ROM, so   */
+/*		we run it from cache.                                        */
+/*                                                                           */
+/* ------------------------------------------------------------------------- */
+
+#include <config.h>
+#include <ppc4xx.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+	.globl  ext_bus_cntlr_init
+ext_bus_cntlr_init:
+	mflr	r4		/* save link register */
+	bl	..getAddr
+..getAddr:
+	mflr	r3		/* get address of ..getAddr */
+	mtlr	r4		/* restore link register */
+	addi	r4,0,14		/* set ctr to 10; used to prefetch */
+	mtctr	r4		/* 10 cache lines to fit this function */
+				/* in cache (gives us 8x10=80 instrctns) */
+..ebcloop:
+	icbt	r0,r3		/* prefetch cache line for addr in r3 */
+	addi	r3,r3,32	/* move to next cache line */
+	bdnz	..ebcloop	/* continue for 10 cache lines */
+
+	/* ----------------------------------------------------------------- */
+	/* Delay to ensure all accesses to ROM are complete before changing  */
+	/* bank 0 timings. 200usec should be enough.			     */
+	/*   200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles	     */
+	/* ----------------------------------------------------------------- */
+	addis	r3,0,0x0
+	ori	r3,r3,0xA000	/* ensure 200usec have passed since reset */
+        mtctr   r3
+..spinlp:
+	bdnz	..spinlp	/* spin loop */
+
+	/* ----------------------------------------------------------------- */
+        /* Set EBC Configuration register				     */
+        /* ----------------------------------------------------------------- */
+
+	addi    r4,0,epcr
+        mtdcr   ebccfga,r4
+	addis   r4,0,PP_CALC_EBC0_CFG(PP_HWID)@h
+	ori     r4,r4,PP_CALC_EBC0_CFG(PP_HWID)@l
+        mtdcr   ebccfgd,r4
+
+        /* ----------------------------------------------------------------- */
+        /* Memory Bank 0 (Flash) initialization (from openbios)		     */
+        /* ----------------------------------------------------------------- */
+
+        addi    r4,0,pb0ap
+        mtdcr   ebccfga,r4
+	addis   r4,0,PP_CALC_EBC0_BnAP(PP_HWID,00)@h
+	ori     r4,r4,PP_CALC_EBC0_BnAP(PP_HWID,00)@l
+        mtdcr   ebccfgd,r4
+
+        addi    r4,0,pb0cr
+        mtdcr   ebccfga,r4
+	addis   r4,0,PP_CALC_EBC0_BnCR(PP_HWID,00)@h
+	ori     r4,r4,PP_CALC_EBC0_BnCR(PP_HWID,00)@l
+        mtdcr   ebccfgd,r4
+
+	nop			/* pass2 DCR errata #8 */
+        blr
+
+/* ------------------------------------------------------------------------- */
+/* Function:     sdram_init						     */
+/* Description:  Dummy implementation here - done in C later		     */
+/* ------------------------------------------------------------------------- */
+	.globl  sdram_init
+sdram_init:
+        mflr    r31
+        
+	/* ----------------------------------------------------------------- */
+	/* Set MB0CF for bank 0.					     */
+	/* ----------------------------------------------------------------- */
+
+        addi    r4,0,mem_mb0cf
+        mtdcr   memcfga,r4
+        addis   r4,0,PP_(SDRAM_B0CR,PP_HWID)@h
+        ori     r4,r4,PP_(SDRAM_B0CR,PP_HWID)@l
+        mtdcr   memcfgd,r4
+
+        /* ----------------------------------------------------------------- */
+	/* Set SDTR1							     */
+        /* ----------------------------------------------------------------- */
+        addis   r6,0,PP_(SDRAM_TR,PP_HWID)@h
+        ori     r6,r6,PP_(SDRAM_TR,PP_HWID)@l
+        addi    r4,0,mem_sdtr1
+        mtdcr   memcfga,r4
+        mtdcr   memcfgd,r6
+
+	/* ----------------------------------------------------------------- */
+	/* Set RTR							     */
+	/* ----------------------------------------------------------------- */
+        addis   r7,0,PP_(SDRAM_RTR,PP_HWID)
+        addi    r4,0,mem_rtr
+        mtdcr   memcfga,r4
+        mtdcr   memcfgd,r7
+
+	/* ----------------------------------------------------------------- */
+	/* Delay to ensure all accesses to ROM are complete before changing  */
+	/* bank 0 timings. 200usec should be enough.			     */
+	/*   200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles	     */
+	/* ----------------------------------------------------------------- */
+	addis	r3,0,0x0
+	ori	r3,r3,0xA000	/* ensure 200usec have passed since reset */
+        mtctr   r3
+..spinlp2:
+	bdnz	..spinlp2	/* spin loop */
+
+	/* ----------------------------------------------------------------- */
+	/* Set memory controller options reg, MCOPT1.			     */
+	/* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst	     */
+	/* read/prefetch.						     */
+	/* ----------------------------------------------------------------- */
+        addi    r4,0,mem_mcopt1
+        mtdcr   memcfga,r4
+        addis   r4,0,0x8080	/* set DC_EN=1 */
+        ori     r4,r4,0x0000
+        mtdcr   memcfgd,r4
+
+	/* ----------------------------------------------------------------- */
+	/* Delay to ensure 10msec have elapsed since reset. This is	     */
+	/* required for the MPC952 to stabalize. Assume worst		     */
+	/* case that the core is running 200Mhz:			     */
+	/* 200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles	     */
+	/* This delay should occur before accessing SDRAM.		     */
+	/* ----------------------------------------------------------------- */
+        addis   r3,0,0x001E
+        ori     r3,r3,0x8480	/* ensure 10msec have passed since reset */
+        mtctr   r3
+..spinlp3:
+        bdnz    ..spinlp3	/* spin loop */
+
+        mtlr    r31		/* restore lr */
+        blr
Index: board/peppercon/peppercon.c
===================================================================
RCS file: board/peppercon/peppercon.c
diff -N board/peppercon/peppercon.c
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ board/peppercon/peppercon.c	24 May 2005 14:01:50 -0000	1.5
@@ -0,0 +1,282 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Derived work: (C) Copyright 2002-2005 Peppercon AG
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include "peppercon.h"
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <ppc4xx.h>
+
+#if (DYNAMIC_PLL == 1)
+# include <i2c.h>
+#endif
+
+#define myendtick(milliseconds) (get_ticks() + (uint64_t)(milliseconds) * (get_tbclk() / 1000))
+
+#ifdef PP_FEAT_USBPOWERED
+# define PP_GPIO_STATUS_LED	9
+static volatile unsigned char led_state = 0;
+#endif
+
+int board_pre_init (void)
+{
+    /* ------------------------------------------------------------------------
+     * Interrupt controller setup
+     */
+
+    mtdcr(uicsr,  0xFFFFFFFF); /* clear all interrupts */
+    mtdcr(uicer,  0x00000000); /* disable all interrupts */
+    mtdcr(uiccr,  0x00000000); /* set all SMI to be non-critical */
+
+    mtdcr(uicpr,  PP_CALC_UIC0_PR(PP_HWID)); /* set polarities */
+    mtdcr(uictr,  PP_CALC_UIC0_TR(PP_HWID)); /* set edge/level characteritics */
+    mtdcr(uicvcr, 0x00000001); /* set vect base=0, INT0 highest priority */
+    mtdcr(uicsr,  0xFFFFFFFF); /* clear all intterrupts */
+
+    /* ------------------------------------------------------------------------
+     * GPIO setup
+     */
+
+    /* configure shared pins */
+#if defined(CONFIG_405GP)
+    mtdcr(0xB1, mfdcr(0xB1) | PP_CALC_CPC0_CR0_GPIO(PP_HWID));
+#elif defined(CONFIG_405EP)
+    
+#endif
+  
+    /* set pegels */
+    out32(GPIO0_OR, PP_CALC_GPIO0_OR(PP_HWID));
+   
+    /* set input/output behavior */
+    out32(GPIO0_TCR, PP_CALC_GPIO0_TCR(PP_HWID));
+
+    /* set open drain behavior */
+    out32(GPIO0_ODR, PP_CALC_GPIO0_ODR(PP_HWID));
+
+#if !defined(CONFIG_405EP)
+    /* ------------------------------------------------------------------------
+     * PHY reset
+     */
+
+    /* we dereference the start address of Chip Select 3 (PHY) */
+    (void)*(volatile ulong*) (PP_CALC_EBC0_BnCR(PP_HWID,03) & 0xFFF00000);
+    sync();
+    udelay(1000);
+#endif /* !CONFIG_405EP */
+
+    return 0;
+}
+
+int board_serial_init (void)
+{
+    gd_t * gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
+    char tmp[11];
+    int serial_debug;
+    int old_baudrate;
+    int i;
+
+    /*
+     * Check if we should output on serial port if a debug cable is found
+     * also decide if to start in restricted user or in devel mode.
+     */
+    i = getenv_r("serial_debug", tmp, sizeof(tmp));
+    gd->devel_mode =
+	serial_debug = (i > 0) ? (int)simple_strtoul(tmp, NULL, 10) : 0;
+
+    /* save current baudrate */
+    old_baudrate = gd->baudrate;
+
+    /*
+     * We always assume a serial debug cable for lara
+     * and never check for a cable kme.
+     */
+    gd->debug_cable_present = 1;
+    gd->serial_debug = serial_debug;
+    gd->cable_kme = 0;
+
+    /* set up serial port for normal use if no cable KME could be found */
+    if (!gd->cable_kme) {
+	gd->baudrate = old_baudrate;
+	serial_init();
+    }
+
+# if !defined(CFG_SERIAL_DEBUG) // sand: @@@ FIXME
+    gd->debug_cable_present = 1;
+    gd->serial_debug = gd->debug_cable_present;
+# endif
+
+    return (0);
+}
+
+#if (DYNAMIC_PLL == 1)
+
+#define PLL_SETTINGS_EQUAL(a0,b0,a1,b1)	(((a0 & 0x00333333) == (b0 & 0x00333333))  &&  \
+					 ((a1 & 0x00F773FF) == (b1 & 0x00F773FF)))
+
+#define RTC_EEP_I2C_ADDR	0x57
+#define SPEED_GRADE_AUTO	0
+#define SPEED_GRADE_SLOW   	1
+#define SPEED_GRADE_FAST	2
+
+static unsigned char
+get_speed_grade_from_eeprom(void)
+{
+    unsigned char val[2];
+    int ret = SPEED_GRADE_AUTO;
+  
+    if (i2c_read(RTC_EEP_I2C_ADDR, 0x0000, 2, val, 2) != 0) {
+	goto bail;	
+    }
+
+    if (val[0] == 0xFF || val[0] == 0x00 ||
+	(val[1] & 0x03) > SPEED_GRADE_FAST) {
+	goto bail;
+    }
+
+    ret = val[1] & 0x03;
+
+ bail:
+    debug("get_speed_grade_from_eeprom %02x\n", ret);
+    return ret;
+}
+
+int
+board_reinit_pll(void)
+{
+    unsigned char speed;
+    unsigned long pllmr0, pllmr1, temp;
+    
+    // determine speed grade we would like to see
+    if ((speed = get_speed_grade_from_eeprom()) == SPEED_GRADE_AUTO) {
+	speed = SPEED_GRADE_FAST; // FIXME, read GPIO in case of AUTO
+    }
+
+    pllmr0 = mfdcr(CPC0_PLLMR0);
+    pllmr1 = mfdcr(CPC0_PLLMR1);
+    
+    if ((speed == SPEED_GRADE_SLOW && PLL_SETTINGS_EQUAL(PLLMR0_SLOW, pllmr0, PLLMR1_SLOW, pllmr1)) ||
+	(speed == SPEED_GRADE_FAST && PLL_SETTINGS_EQUAL(PLLMR0_FAST, pllmr0, PLLMR1_FAST, pllmr1))) {
+
+	return 0;
+    }
+
+    printf("Reinitializing PLL\n");
+    if (speed == SPEED_GRADE_SLOW) {
+	pllmr0 = PLLMR0_SLOW;
+	pllmr1 = PLLMR1_SLOW;
+    } else {
+	pllmr0 = PLLMR0_FAST;
+	pllmr1 = PLLMR1_FAST;
+    }
+
+    // reprogram the PLL and reset again
+    mtdcr(CPC0_UCR, (mfdcr(CPC0_UCR) & 0xFFFF0000) | 0x00000101); // stop UART clock
+
+    // reset and disable PLL
+    temp = mfdcr(CPC0_PLLMR1) & 0x7FFFFFFF;
+    mtdcr(CPC0_PLLMR1, temp);
+    temp |= 0x40000000;
+    mtdcr(CPC0_PLLMR1, temp);
+
+    // set new dividers
+    mtdcr(CPC0_PLLMR0, pllmr0);
+    temp = (pllmr1 & 0x3FFFFFFF) | 0x40000000;
+    mtdcr(CPC0_PLLMR1, temp);
+ 
+    // clear PLL reset, wait and enable it
+    temp &= 0xBFFFFFFF;
+    mtdcr(CPC0_PLLMR1, temp);
+    udelay(100);
+    temp |= 0x80000000;
+    mtdcr(CPC0_PLLMR1, temp);
+
+    // reset core, cu later
+    mtspr(dbcr0, 0x10000000);
+    
+    /* NOTREACHED */
+    return 0;
+}
+
+#endif
+
+#ifdef PP_FEAT_USBPOWERED
+void
+toggle_led_state(void)
+{
+    ulong iflag = disable_interrupts();
+    
+    /*	  
+      Let the status LED on GPIO9 blink on LARA XP boards.
+      Its ugly here, but its just a stupid LED for now.
+      Next time we need periodic events I'll implement a
+      timer queue...
+    */
+    unsigned long reg = in32(GPIO0_OR);
+    reg &= ~(1 << (31 - PP_GPIO_STATUS_LED));
+    reg |= ((led_state) << (31 - PP_GPIO_STATUS_LED));
+    out32(GPIO0_OR, reg);
+    led_state = (led_state) ? 0 : 1;
+    
+    if (iflag) enable_interrupts();
+}
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+unsigned char checkboard (void)
+{  
+    /*
+      this doesn't work because of b0rken hardware (no bus driver)
+      
+      hw_id_addr = (unsigned char *) 0xF0600000;
+    */
+
+    printf ("HWID:  %02x - %s\n", PP_HWID_INT, PP_HW_DESCRIPTION(PP_HWID));
+
+    return PP_HWID_INT;
+}
+
+long int initdram (int board_type)
+{
+    /* return the SDRAM size */
+    return ((1 << (((PP_(SDRAM_B0CR, PP_HWID) >> 17) & 0x7) + 2)) * 1024 * 1024);
+}
+
+/* ------------------------------------------------------------------------- */
+
+int testdram (void)
+{
+    /* TODO: XXX XXX XXX */
+    printf ("test: xxx MB - ok\n");
+
+    return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
Index: board/peppercon/peppercon.h
===================================================================
RCS file: board/peppercon/peppercon.h
diff -N board/peppercon/peppercon.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ board/peppercon/peppercon.h	29 Apr 2005 08:43:29 -0000	1.4
@@ -0,0 +1,511 @@
+#ifndef _PEPPERCON_H
+#define _PEPPERCON_H
+
+/*
+ * Include hardware definitions.
+ */
+#include "hw_0E.h"
+#include "hw_0F.h"
+#include "hw_10.h"
+#include "hw_11.h"
+#include "hw_12.h"
+
+/*
+ * Processor types
+ */
+#define PP_CPU_405GP	1
+#define PP_CPU_405EP	2
+
+/*
+ * serial lines
+ */
+#define PP_SERIAL_0     0
+#define PP_SERIAL_1     1
+
+/*
+ * Generic macro for getting hardware id specific values.
+ *
+ * NOTES: - Hardware ids are always two characters wide - possibly
+ *	    with leading zeros.
+ *
+ *	  - The routine is wrapped to ensure that the arguments get
+ *          expanded first.
+ *
+ *	  - The "name" parameter must not be macro expanded!
+ */
+#define PP_(name, hwid) __PP_PREFIX(_##name, hwid)
+#define __PP_PREFIX(name, hwid) PP_HWID_##hwid##name
+
+/*
+ * Texttual description of the hardware
+ *
+ * NOTES: - Hardware ids are always two characters wide - possibly
+ *	    with leading zeros.
+ *
+ *	  - The routine is wrapped to ensure that the arguments get
+ *          expanded first.
+ */
+#define PP_HW_DESCRIPTION(hwid) __PP_HW_DESCRIPTION(hwid)
+#define __PP_HW_DESCRIPTION(hwid) PP_HWID_##hwid##_DESCRIPTION
+
+/*
+ * Calculate the EBC Configuration Register (EBC0_CFG) for a given hardware id.
+ *
+ * NOTES: - Hardware ids are always two characters wide - possibly
+ *	    with leading zeros.
+ *
+ *	  - The routine is wrapped to ensure that the arguments get
+ *          expanded first.
+ */
+#define PP_CALC_EBC0_CFG(hwid) __PP_CALC_EBC0_CFG(hwid)
+#define __PP_CALC_EBC0_CFG(hwid)				   \
+    (((PP_HWID_##hwid##_EBC_CFG_EBTC   & 0x01) << (31-0))  \
+     | ((PP_HWID_##hwid##_EBC_CFG_PTD  & 0x01) << (31-1))  \
+     | ((PP_HWID_##hwid##_EBC_CFG_RTC  & 0x07) << (31-4))  \
+     | ((PP_HWID_##hwid##_EBC_CFG_EMPL & 0x03) << (31-6))  \
+     | ((PP_HWID_##hwid##_EBC_CFG_EMPH & 0x03) << (31-8))  \
+     | ((PP_HWID_##hwid##_EBC_CFG_CSTC & 0x01) << (31-9))  \
+     | ((PP_HWID_##hwid##_EBC_CFG_BPF  & 0x03) << (31-11)) \
+     | ((PP_HWID_##hwid##_EBC_CFG_EMS  & 0x03) << (31-13)) \
+     | ((PP_HWID_##hwid##_EBC_CFG_PME  & 0x01) << (31-14)) \
+     | ((PP_HWID_##hwid##_EBC_CFG_PMT  & 0x1f) << (31-19)))
+
+/*
+ * Calculate the Peripheral Bank Access Parameters (EBC0_BnAP)
+ * for a given hardware id and bank number.
+ *
+ * NOTES: - Hardware ids and bank numbers are always two characters
+ *	    wide - possibly with leading zeros.
+ *
+ *	  - The routine is wrapped to ensure that the arguments get
+ *          expanded first.
+ */
+#define PP_CALC_EBC0_BnAP(hwid, bank) __PP_CALC_EBC0_BnAP(hwid, bank)
+#define __PP_CALC_EBC0_BnAP(hwid, bank)					\
+    (((PP_HWID_##hwid##_CS_##bank##_AP_BME   & 0x01) << (31-0))		\
+     | ((PP_HWID_##hwid##_CS_##bank##_AP_TWT & 0xff &			\
+	 ((PP_HWID_##hwid##_CS_##bank##_AP_BME & 0x1) - 1)) << (31-8))	\
+     | (((PP_HWID_##hwid##_CS_##bank##_AP_FWT   & 0x1f &		\
+	  (0 - (PP_HWID_##hwid##_CS_##bank##_AP_BME & 0x1))) << (31-5))	\
+	| ((PP_HWID_##hwid##_CS_##bank##_AP_BWT & 0x07 &		\
+	    (0 - (PP_HWID_##hwid##_CS_##bank##_AP_BME & 0x1))) << (31-8))) \
+     | ((PP_HWID_##hwid##_CS_##bank##_AP_CSN & 0x03) << (31-13))	\
+     | ((PP_HWID_##hwid##_CS_##bank##_AP_OEN & 0x03) << (31-15))	\
+     | ((PP_HWID_##hwid##_CS_##bank##_AP_WBN & 0x03) << (31-17))	\
+     | ((PP_HWID_##hwid##_CS_##bank##_AP_WBF & 0x03) << (31-19))	\
+     | ((PP_HWID_##hwid##_CS_##bank##_AP_TH  & 0x07) << (31-22))	\
+     | ((PP_HWID_##hwid##_CS_##bank##_AP_RE  & 0x01) << (31-23))	\
+     | ((PP_HWID_##hwid##_CS_##bank##_AP_SOR & 0x01) << (31-24))	\
+     | ((PP_HWID_##hwid##_CS_##bank##_AP_BEM & 0x01) << (31-25))	\
+     | ((PP_HWID_##hwid##_CS_##bank##_AP_PEN & 0x01) << (31-26)))
+
+/*
+ * Calculate the Peripheral Bank Configuration Register (EBC0_BnCR)
+ * for a given hardware id and bank number.
+ *
+ * NOTES: - Hardware ids and bank numbers are always two characters
+ *	    wide - possibly with leading zeros.
+ *
+ *	  - The routine is wrapped to ensure that the arguments get
+ *          expanded first.
+ */
+#define PP_CALC_EBC0_BnCR(hwid, bank) __PP_CALC_EBC0_BnCR(hwid, bank)
+#define __PP_CALC_EBC0_BnCR(hwid, bank)				\
+    ((PP_HWID_##hwid##_CS_##bank##_CR_BAS   & 0xFFF00000)	\
+     | ((PP_HWID_##hwid##_CS_##bank##_CR_BS & 0x7) << (31-14))	\
+     | ((PP_HWID_##hwid##_CS_##bank##_CR_BU & 0x3) << (31-16))	\
+     | ((PP_HWID_##hwid##_CS_##bank##_CR_BW & 0x3) << (31-18)))
+
+/*
+ * Calculate the UIC Polarity Register (UIC0_PR) for a given hardware id.
+ *
+ * NOTES: - Internal interrupts are set to positive polarity.
+ *	    (PPC405GP manual 10.5.4)
+ *
+ *        - Hardware ids are always two characters wide - possibly
+ *	    with leading zeros.
+ *
+ *	  - The routine is wrapped to ensure that the arguments get
+ *          expanded first.
+ */
+#define PP_CALC_UIC0_PR(hwid) __PP_CALC_UIC0_PR(hwid)
+#define __PP_CALC_UIC0_PR(hwid)						\
+    (0xFFFFFF80								\
+     | ((PP_HWID_##hwid##_EXT_IRQ_00_HAS_POS_POLARITY & 0x1) << (31-25)) \
+     | ((PP_HWID_##hwid##_EXT_IRQ_01_HAS_POS_POLARITY & 0x1) << (31-26)) \
+     | ((PP_HWID_##hwid##_EXT_IRQ_02_HAS_POS_POLARITY & 0x1) << (31-27)) \
+     | ((PP_HWID_##hwid##_EXT_IRQ_03_HAS_POS_POLARITY & 0x1) << (31-28)) \
+     | ((PP_HWID_##hwid##_EXT_IRQ_04_HAS_POS_POLARITY & 0x1) << (31-29)) \
+     | ((PP_HWID_##hwid##_EXT_IRQ_05_HAS_POS_POLARITY & 0x1) << (31-30)) \
+     | ((PP_HWID_##hwid##_EXT_IRQ_06_HAS_POS_POLARITY & 0x1) << (31-31)))
+
+/*
+ * Calculate the UIC Trigger Register (UIC0_TR) for a given hardware id.
+ *
+ * NOTES: - Internal interrupts are set to level sensitive and the
+ *	    external master interrupt is edge sensitive.
+ *	    (PPC405GP manual 10.5.5)
+ *
+ *        - Hardware ids are always two characters wide - possibly
+ *	    with leading zeros.
+ *
+ *	  - The routine is wrapped to ensure that the arguments get
+ *          expanded first.
+ */
+#define PP_CALC_UIC0_TR(hwid) __PP_CALC_UIC0_TR(hwid)
+#define __PP_CALC_UIC0_TR(hwid)						\
+    (0x10000000								\
+     | ((PP_HWID_##hwid##_EXT_IRQ_00_IS_EDGE_TRIGGERED & 0x1) << (31-25)) \
+     | ((PP_HWID_##hwid##_EXT_IRQ_01_IS_EDGE_TRIGGERED & 0x1) << (31-26)) \
+     | ((PP_HWID_##hwid##_EXT_IRQ_02_IS_EDGE_TRIGGERED & 0x1) << (31-27)) \
+     | ((PP_HWID_##hwid##_EXT_IRQ_03_IS_EDGE_TRIGGERED & 0x1) << (31-28)) \
+     | ((PP_HWID_##hwid##_EXT_IRQ_04_IS_EDGE_TRIGGERED & 0x1) << (31-29)) \
+     | ((PP_HWID_##hwid##_EXT_IRQ_05_IS_EDGE_TRIGGERED & 0x1) << (31-30)) \
+     | ((PP_HWID_##hwid##_EXT_IRQ_06_IS_EDGE_TRIGGERED & 0x1) << (31-31)))
+
+/*
+ * Calculate the GPIO part of the Chip Control Register 0 (CPC0_CR0)
+ * for a given hardware id.
+ *
+ * NOTES: - PPC405EP should not use this routine since a different
+ *	    configuration mechanism is used.
+ *
+ *	  - Hardware ids are always two characters wide - possibly
+ *	    with leading zeros.
+ *
+ *	  - The routine is wrapped to ensure that the arguments get
+ *          expanded first.
+ */
+#if PP_(CPU_TYPE, PP_HWID) != PP_CPU_405EP
+# define PP_CALC_CPC0_CR0_GPIO(hwid) __PP_CALC_CPC0_CR0_GPIO(hwid)
+# define __PP_CALC_CPC0_CR0_GPIO(hwid)				\
+    (((PP_HWID_##hwid##_GPIO_10_IS_GPIO & 0x1) << (31-5))	\
+     | ((PP_HWID_##hwid##_GPIO_11_IS_GPIO & 0x1) << (31-6))	\
+     | ((PP_HWID_##hwid##_GPIO_12_IS_GPIO & 0x1) << (31-7))	\
+     | ((PP_HWID_##hwid##_GPIO_13_IS_GPIO & 0x1) << (31-8))	\
+     | ((PP_HWID_##hwid##_GPIO_14_IS_GPIO & 0x1) << (31-9))	\
+     | ((PP_HWID_##hwid##_GPIO_15_IS_GPIO & 0x1) << (31-10))	\
+     | ((PP_HWID_##hwid##_GPIO_16_IS_GPIO & 0x1) << (31-11))	\
+     | ((PP_HWID_##hwid##_GPIO_17_IS_GPIO & 0x1) << (31-12))	\
+     | ((PP_HWID_##hwid##_GPIO_18_IS_GPIO & 0x1) << (31-13))	\
+     | ((PP_HWID_##hwid##_GPIO_19_IS_GPIO & 0x1) << (31-14))	\
+     | ((PP_HWID_##hwid##_GPIO_20_IS_GPIO & 0x1) << (31-15))	\
+     | ((PP_HWID_##hwid##_GPIO_21_IS_GPIO & 0x1) << (31-16))	\
+     | ((PP_HWID_##hwid##_GPIO_22_IS_GPIO & 0x1) << (31-17))	\
+     | ((PP_HWID_##hwid##_GPIO_23_IS_GPIO & 0x1) << (31-18)))
+#endif /* !PP_CPU_405EP */
+
+/*
+ * Calculate the GPIO Output Select Registers (GPIO0_OSRH and GPIO0_OSRL)
+ * for a given hardware id.
+ *
+ * NOTES: - Only PPC405EP should use this routine since a different
+ *	    configuration mechanism is used on other processors.
+ *
+ *	  - Hardware ids are always two characters wide - possibly
+ *	    with leading zeros.
+ *
+ *	  - The routine is wrapped to ensure that the arguments get
+ *          expanded first.
+ */
+#if PP_(CPU_TYPE, PP_HWID) == PP_CPU_405EP
+# define PP_CALC_GPIO0_OSRH(hwid) __PP_CALC_GPIO0_OSRH(hwid)
+# define __PP_CALC_GPIO0_OSRH(hwid)					\
+    ((((PP_HWID_##hwid##_GPIO_00_IS_GPIO & 0x1) ^ 0x1) << (31-1))	\
+     | (((PP_HWID_##hwid##_GPIO_01_IS_GPIO & 0x1) ^ 0x1) << (31-3))	\
+     | (((PP_HWID_##hwid##_GPIO_02_IS_GPIO & 0x1) ^ 0x1) << (31-5))	\
+     | (((PP_HWID_##hwid##_GPIO_03_IS_GPIO & 0x1) ^ 0x1) << (31-7))	\
+     | (((PP_HWID_##hwid##_GPIO_04_IS_GPIO & 0x1) ^ 0x1) << (31-9))	\
+     | (((PP_HWID_##hwid##_GPIO_05_IS_GPIO & 0x1) ^ 0x1) << (31-11))	\
+     | (((PP_HWID_##hwid##_GPIO_06_IS_GPIO & 0x1) ^ 0x1) << (31-13))	\
+     | (((PP_HWID_##hwid##_GPIO_07_IS_GPIO & 0x1) ^ 0x1) << (31-15))	\
+     | (((PP_HWID_##hwid##_GPIO_08_IS_GPIO & 0x1) ^ 0x1) << (31-17))	\
+     | (((PP_HWID_##hwid##_GPIO_09_IS_GPIO & 0x1) ^ 0x1) << (31-19))	\
+     | (((PP_HWID_##hwid##_GPIO_10_IS_GPIO & 0x1) ^ 0x1) << (31-21))	\
+     | (((PP_HWID_##hwid##_GPIO_11_IS_GPIO & 0x1) ^ 0x1) << (31-23))	\
+     | (((PP_HWID_##hwid##_GPIO_12_IS_GPIO & 0x1) ^ 0x1) << (31-25))	\
+     | (((PP_HWID_##hwid##_GPIO_13_IS_GPIO & 0x1) ^ 0x1) << (31-27))	\
+     | (((PP_HWID_##hwid##_GPIO_14_IS_GPIO & 0x1) ^ 0x1) << (31-29))	\
+     | (((PP_HWID_##hwid##_GPIO_15_IS_GPIO & 0x1) ^ 0x1) << (31-31)))
+# define PP_CALC_GPIO0_OSRL(hwid) __PP_CALC_GPIO0_OSRL(hwid)
+# define __PP_CALC_GPIO0_OSRL(hwid)					\
+    ((((PP_HWID_##hwid##_GPIO_16_IS_GPIO & 0x1) ^ 0x1) << (31-1))	\
+     | (((PP_HWID_##hwid##_GPIO_17_IS_GPIO & 0x1) ^ 0x1) << (31-3))	\
+     | (((PP_HWID_##hwid##_GPIO_18_IS_GPIO & 0x1) ^ 0x1) << (31-5))	\
+     | (((PP_HWID_##hwid##_GPIO_19_IS_GPIO & 0x1) ^ 0x1) << (31-7))	\
+     | (((PP_HWID_##hwid##_GPIO_20_IS_GPIO & 0x1) ^ 0x1) << (31-9))	\
+     | (((PP_HWID_##hwid##_GPIO_21_IS_GPIO & 0x1) ^ 0x1) << (31-11))	\
+     | (((PP_HWID_##hwid##_GPIO_22_IS_GPIO & 0x1) ^ 0x1) << (31-13))	\
+     | (((PP_HWID_##hwid##_GPIO_23_IS_GPIO & 0x1) ^ 0x1) << (31-15))	\
+     | (((PP_HWID_##hwid##_GPIO_24_IS_GPIO & 0x1) ^ 0x1) << (31-17))	\
+     | (((PP_HWID_##hwid##_GPIO_25_IS_GPIO & 0x1) ^ 0x1) << (31-19))	\
+     | (((PP_HWID_##hwid##_GPIO_26_IS_GPIO & 0x1) ^ 0x1) << (31-21))	\
+     | (((PP_HWID_##hwid##_GPIO_27_IS_GPIO & 0x1) ^ 0x1) << (31-23))							\
+     | (((PP_HWID_##hwid##_GPIO_28_IS_GPIO & 0x1) ^ 0x1) << (31-25))							\
+     | (((PP_HWID_##hwid##_GPIO_29_IS_GPIO & 0x1) ^ 0x1) << (31-27))							\
+     | (((PP_HWID_##hwid##_GPIO_30_IS_GPIO & 0x1) ^ 0x1) << (31-29))							\
+     | (((PP_HWID_##hwid##_GPIO_31_IS_GPIO & 0x1) ^ 0x1) << (31-31)))
+#endif /* PP_CPU_405EP */
+
+/*
+ * Determine if a GPIO pin needs to be configured as output. On the
+ * PPC405EP we have to respect the alternate PIN configuration as
+ * shown in the PPC405EP user manual under section 23.6.1.
+ */
+#if PP_(CPU_TYPE, PP_HWID) == PP_CPU_405EP
+# define _PP_GPIO_IS_OUTPUT(hwid, gpio)				\
+    (((PP_HWID_##hwid##_GPIO_##gpio##_IS_GPIO & 0x1)		\
+      & (PP_HWID_##hwid##_GPIO_##gpio##_IS_OUTPUT & 0x1))	\
+     | (~(PP_HWID_##hwid##_GPIO_##gpio##_IS_GPIO & 0x1)		\
+	& (PP_GPIO_##gpio##_TCR_DEFAULT & 0x1)))
+#else
+# define _PP_GPIO_IS_OUTPUT(hwid, gpio)				\
+    ((PP_HWID_##hwid##_GPIO_##gpio##_IS_GPIO & 0x1) &		\
+     (PP_HWID_##hwid##_GPIO_##gpio##_IS_OUTPUT & 0x1))
+#endif
+
+/*
+ * The defaults for the GPIO Three-State Control Register (GPIO0_TCR)
+ * on a PPC405EP.
+ */
+#if PP_(CPU_TYPE, PP_HWID) == PP_CPU_405EP
+# define PP_GPIO_00_TCR_DEFAULT	1
+# define PP_GPIO_01_TCR_DEFAULT	1
+# define PP_GPIO_02_TCR_DEFAULT	1
+# define PP_GPIO_03_TCR_DEFAULT	1
+# define PP_GPIO_04_TCR_DEFAULT	1
+# define PP_GPIO_05_TCR_DEFAULT	1
+# define PP_GPIO_06_TCR_DEFAULT	1
+# define PP_GPIO_07_TCR_DEFAULT	1
+# define PP_GPIO_08_TCR_DEFAULT	1
+# define PP_GPIO_09_TCR_DEFAULT	1
+# define PP_GPIO_10_TCR_DEFAULT	1
+# define PP_GPIO_11_TCR_DEFAULT	1
+# define PP_GPIO_12_TCR_DEFAULT	1
+# define PP_GPIO_13_TCR_DEFAULT	1
+# define PP_GPIO_14_TCR_DEFAULT	1
+# define PP_GPIO_15_TCR_DEFAULT	1
+# define PP_GPIO_16_TCR_DEFAULT	1
+# define PP_GPIO_17_TCR_DEFAULT	0
+# define PP_GPIO_18_TCR_DEFAULT	0
+# define PP_GPIO_19_TCR_DEFAULT	0
+# define PP_GPIO_20_TCR_DEFAULT	0
+# define PP_GPIO_21_TCR_DEFAULT	0
+# define PP_GPIO_22_TCR_DEFAULT	0
+# define PP_GPIO_23_TCR_DEFAULT	0
+# define PP_GPIO_24_TCR_DEFAULT	0
+# define PP_GPIO_25_TCR_DEFAULT	0
+# define PP_GPIO_26_TCR_DEFAULT	0
+# define PP_GPIO_27_TCR_DEFAULT	1
+# define PP_GPIO_28_TCR_DEFAULT	0
+# define PP_GPIO_29_TCR_DEFAULT	1
+# define PP_GPIO_30_TCR_DEFAULT	0
+# define PP_GPIO_31_TCR_DEFAULT	0
+#endif
+
+/*
+ * Calculate the GPIO Three-State Control Register (GPIO0_TCR)
+ * for a given hardware id.
+ *
+ * NOTES: - Hardware ids are always two characters wide - possibly
+ *	    with leading zeros.
+ *
+ *	  - The routine is wrapped to ensure that the arguments get
+ *          expanded first.
+ */
+#define PP_CALC_GPIO0_TCR(hwid) __PP_CALC_GPIO0_TCR(hwid)
+#define __PP_CALC_GPIO0_TCR(hwid)				\
+    (_PP_GPIO0_TCR_405EP_EXT(hwid)				\
+     | ((_PP_GPIO_IS_OUTPUT(hwid, 01) & 0x1) << (31-1))		\
+     | ((_PP_GPIO_IS_OUTPUT(hwid, 02) & 0x1) << (31-2))		\
+     | ((_PP_GPIO_IS_OUTPUT(hwid, 03) & 0x1) << (31-3))		\
+     | ((_PP_GPIO_IS_OUTPUT(hwid, 04) & 0x1) << (31-4))		\
+     | ((_PP_GPIO_IS_OUTPUT(hwid, 05) & 0x1) << (31-5))		\
+     | ((_PP_GPIO_IS_OUTPUT(hwid, 06) & 0x1) << (31-6))		\
+     | ((_PP_GPIO_IS_OUTPUT(hwid, 07) & 0x1) << (31-7))		\
+     | ((_PP_GPIO_IS_OUTPUT(hwid, 08) & 0x1) << (31-8))		\
+     | ((_PP_GPIO_IS_OUTPUT(hwid, 09) & 0x1) << (31-9))		\
+     | ((_PP_GPIO_IS_OUTPUT(hwid, 10) & 0x1) << (31-10))	\
+     | ((_PP_GPIO_IS_OUTPUT(hwid, 11) & 0x1) << (31-11))	\
+     | ((_PP_GPIO_IS_OUTPUT(hwid, 12) & 0x1) << (31-12))	\
+     | ((_PP_GPIO_IS_OUTPUT(hwid, 13) & 0x1) << (31-13))	\
+     | ((_PP_GPIO_IS_OUTPUT(hwid, 14) & 0x1) << (31-14))	\
+     | ((_PP_GPIO_IS_OUTPUT(hwid, 15) & 0x1) << (31-15))	\
+     | ((_PP_GPIO_IS_OUTPUT(hwid, 16) & 0x1) << (31-16))	\
+     | ((_PP_GPIO_IS_OUTPUT(hwid, 17) & 0x1) << (31-17))	\
+     | ((_PP_GPIO_IS_OUTPUT(hwid, 18) & 0x1) << (31-18))	\
+     | ((_PP_GPIO_IS_OUTPUT(hwid, 19) & 0x1) << (31-19))	\
+     | ((_PP_GPIO_IS_OUTPUT(hwid, 20) & 0x1) << (31-20))	\
+     | ((_PP_GPIO_IS_OUTPUT(hwid, 21) & 0x1) << (31-21))	\
+     | ((_PP_GPIO_IS_OUTPUT(hwid, 22) & 0x1) << (31-22))	\
+     | ((_PP_GPIO_IS_OUTPUT(hwid, 23) & 0x1) << (31-23)))
+/* PPC405_EP extensions */
+#if PP_(CPU_TYPE, PP_HWID) == PP_CPU_405EP
+# define _PP_GPIO0_TCR_405EP_EXT(hwid)				\
+    (((_PP_GPIO_IS_OUTPUT(hwid, 00) & 0x1) << (31-0))		\
+     | ((_PP_GPIO_IS_OUTPUT(hwid, 24) & 0x1) << (31-24))	\
+     | ((_PP_GPIO_IS_OUTPUT(hwid, 25) & 0x1) << (31-25))	\
+     | ((_PP_GPIO_IS_OUTPUT(hwid, 26) & 0x1) << (31-26))	\
+     | ((_PP_GPIO_IS_OUTPUT(hwid, 27) & 0x1) << (31-27))	\
+     | ((_PP_GPIO_IS_OUTPUT(hwid, 28) & 0x1) << (31-28))	\
+     | ((_PP_GPIO_IS_OUTPUT(hwid, 29) & 0x1) << (31-29))	\
+     | ((_PP_GPIO_IS_OUTPUT(hwid, 30) & 0x1) << (31-30))	\
+     | ((_PP_GPIO_IS_OUTPUT(hwid, 31) & 0x1) << (31-31)))
+#else
+# define _PP_GPIO0_TCR_405EP_EXT(hwid) 0x0
+#endif
+
+/*
+ * Calculate the GPIO Open Drain Register (GPIO0_ODR) for a given hardware id.
+ *
+ * NOTES: - Hardware ids are always two characters wide - possibly
+ *	    with leading zeros.
+ *
+ *	  - The routine is wrapped to ensure that the arguments get
+ *          expanded first.
+ */
+#define PP_CALC_GPIO0_ODR(hwid) __PP_CALC_GPIO0_ODR(hwid)
+#define __PP_CALC_GPIO0_ODR(hwid)					\
+    (_PP_GPIO0_ODR_405EP_EXT(hwid)					\
+     | ((PP_HWID_##hwid##_GPIO_01_IS_OPEN_DRAIN & 0x1) << (31-1))	\
+     | ((PP_HWID_##hwid##_GPIO_02_IS_OPEN_DRAIN & 0x1) << (31-2))	\
+     | ((PP_HWID_##hwid##_GPIO_03_IS_OPEN_DRAIN & 0x1) << (31-3))	\
+     | ((PP_HWID_##hwid##_GPIO_04_IS_OPEN_DRAIN & 0x1) << (31-4))	\
+     | ((PP_HWID_##hwid##_GPIO_05_IS_OPEN_DRAIN & 0x1) << (31-5))	\
+     | ((PP_HWID_##hwid##_GPIO_06_IS_OPEN_DRAIN & 0x1) << (31-6))	\
+     | ((PP_HWID_##hwid##_GPIO_07_IS_OPEN_DRAIN & 0x1) << (31-7))	\
+     | ((PP_HWID_##hwid##_GPIO_08_IS_OPEN_DRAIN & 0x1) << (31-8))	\
+     | ((PP_HWID_##hwid##_GPIO_09_IS_OPEN_DRAIN & 0x1) << (31-9))	\
+     | ((PP_HWID_##hwid##_GPIO_10_IS_OPEN_DRAIN & 0x1) << (31-10))	\
+     | ((PP_HWID_##hwid##_GPIO_11_IS_OPEN_DRAIN & 0x1) << (31-11))	\
+     | ((PP_HWID_##hwid##_GPIO_12_IS_OPEN_DRAIN & 0x1) << (31-12))	\
+     | ((PP_HWID_##hwid##_GPIO_13_IS_OPEN_DRAIN & 0x1) << (31-13))	\
+     | ((PP_HWID_##hwid##_GPIO_14_IS_OPEN_DRAIN & 0x1) << (31-14))	\
+     | ((PP_HWID_##hwid##_GPIO_15_IS_OPEN_DRAIN & 0x1) << (31-15))	\
+     | ((PP_HWID_##hwid##_GPIO_16_IS_OPEN_DRAIN & 0x1) << (31-16))	\
+     | ((PP_HWID_##hwid##_GPIO_17_IS_OPEN_DRAIN & 0x1) << (31-17))	\
+     | ((PP_HWID_##hwid##_GPIO_18_IS_OPEN_DRAIN & 0x1) << (31-18))	\
+     | ((PP_HWID_##hwid##_GPIO_19_IS_OPEN_DRAIN & 0x1) << (31-19))	\
+     | ((PP_HWID_##hwid##_GPIO_20_IS_OPEN_DRAIN & 0x1) << (31-20))	\
+     | ((PP_HWID_##hwid##_GPIO_21_IS_OPEN_DRAIN & 0x1) << (31-21))	\
+     | ((PP_HWID_##hwid##_GPIO_22_IS_OPEN_DRAIN & 0x1) << (31-22))	\
+     | ((PP_HWID_##hwid##_GPIO_23_IS_OPEN_DRAIN & 0x1) << (31-23)))
+/* PPC405_EP extensions */
+#if PP_(CPU_TYPE, PP_HWID) == PP_CPU_405EP
+# define _PP_GPIO0_ODR_405EP_EXT(hwid)					\
+    (((PP_HWID_##hwid##_GPIO_00_IS_OPEN_DRAIN & 0x1) << (31-0))		\
+     | ((PP_HWID_##hwid##_GPIO_24_IS_OPEN_DRAIN & 0x1) << (31-24))	\
+     | ((PP_HWID_##hwid##_GPIO_25_IS_OPEN_DRAIN & 0x1) << (31-25))	\
+     | ((PP_HWID_##hwid##_GPIO_26_IS_OPEN_DRAIN & 0x1) << (31-26))	\
+     | ((PP_HWID_##hwid##_GPIO_27_IS_OPEN_DRAIN & 0x1) << (31-27))	\
+     | ((PP_HWID_##hwid##_GPIO_28_IS_OPEN_DRAIN & 0x1) << (31-28))	\
+     | ((PP_HWID_##hwid##_GPIO_29_IS_OPEN_DRAIN & 0x1) << (31-29))	\
+     | ((PP_HWID_##hwid##_GPIO_30_IS_OPEN_DRAIN & 0x1) << (31-30))	\
+     | ((PP_HWID_##hwid##_GPIO_31_IS_OPEN_DRAIN & 0x1) << (31-31)))
+#else
+# define _PP_GPIO0_ODR_405EP_EXT(hwid) 0x0
+#endif
+
+/*
+ * Calculate the GPIO Output Register (GPIO0_OR) for a given hardware id.
+ *
+ * NOTES: - Hardware ids are always two characters wide - possibly
+ *	    with leading zeros.
+ *
+ *	  - The routine is wrapped to ensure that the arguments get
+ *          expanded first.
+ */
+#define PP_CALC_GPIO0_OR(hwid) __PP_CALC_GPIO0_OR(hwid)
+#define __PP_CALC_GPIO0_OR(hwid)					\
+    (_PP_GPIO0_OR_405EP_EXT(hwid)					\
+     | ((PP_HWID_##hwid##_GPIO_01_OUTPUT_VALUE & 0x1) << (31-1))	\
+     | ((PP_HWID_##hwid##_GPIO_02_OUTPUT_VALUE & 0x1) << (31-2))	\
+     | ((PP_HWID_##hwid##_GPIO_03_OUTPUT_VALUE & 0x1) << (31-3))	\
+     | ((PP_HWID_##hwid##_GPIO_04_OUTPUT_VALUE & 0x1) << (31-4))	\
+     | ((PP_HWID_##hwid##_GPIO_05_OUTPUT_VALUE & 0x1) << (31-5))	\
+     | ((PP_HWID_##hwid##_GPIO_06_OUTPUT_VALUE & 0x1) << (31-6))	\
+     | ((PP_HWID_##hwid##_GPIO_07_OUTPUT_VALUE & 0x1) << (31-7))	\
+     | ((PP_HWID_##hwid##_GPIO_08_OUTPUT_VALUE & 0x1) << (31-8))	\
+     | ((PP_HWID_##hwid##_GPIO_09_OUTPUT_VALUE & 0x1) << (31-9))	\
+     | ((PP_HWID_##hwid##_GPIO_10_OUTPUT_VALUE & 0x1) << (31-10))	\
+     | ((PP_HWID_##hwid##_GPIO_11_OUTPUT_VALUE & 0x1) << (31-11))	\
+     | ((PP_HWID_##hwid##_GPIO_12_OUTPUT_VALUE & 0x1) << (31-12))	\
+     | ((PP_HWID_##hwid##_GPIO_13_OUTPUT_VALUE & 0x1) << (31-13))	\
+     | ((PP_HWID_##hwid##_GPIO_14_OUTPUT_VALUE & 0x1) << (31-14))	\
+     | ((PP_HWID_##hwid##_GPIO_15_OUTPUT_VALUE & 0x1) << (31-15))	\
+     | ((PP_HWID_##hwid##_GPIO_16_OUTPUT_VALUE & 0x1) << (31-16))	\
+     | ((PP_HWID_##hwid##_GPIO_17_OUTPUT_VALUE & 0x1) << (31-17))	\
+     | ((PP_HWID_##hwid##_GPIO_18_OUTPUT_VALUE & 0x1) << (31-18))	\
+     | ((PP_HWID_##hwid##_GPIO_19_OUTPUT_VALUE & 0x1) << (31-19))	\
+     | ((PP_HWID_##hwid##_GPIO_20_OUTPUT_VALUE & 0x1) << (31-20))	\
+     | ((PP_HWID_##hwid##_GPIO_21_OUTPUT_VALUE & 0x1) << (31-21))	\
+     | ((PP_HWID_##hwid##_GPIO_22_OUTPUT_VALUE & 0x1) << (31-22))	\
+     | ((PP_HWID_##hwid##_GPIO_23_OUTPUT_VALUE & 0x1) << (31-23)))
+/* PPC405_EP extensions */
+#if PP_(CPU_TYPE, PP_HWID) == PP_CPU_405EP
+# define _PP_GPIO0_OR_405EP_EXT(hwid)					\
+    (((PP_HWID_##hwid##_GPIO_00_OUTPUT_VALUE & 0x1) << (31-0))		\
+     | ((PP_HWID_##hwid##_GPIO_24_OUTPUT_VALUE & 0x1) << (31-24))	\
+     | ((PP_HWID_##hwid##_GPIO_25_OUTPUT_VALUE & 0x1) << (31-25))	\
+     | ((PP_HWID_##hwid##_GPIO_26_OUTPUT_VALUE & 0x1) << (31-26))	\
+     | ((PP_HWID_##hwid##_GPIO_27_OUTPUT_VALUE & 0x1) << (31-27))	\
+     | ((PP_HWID_##hwid##_GPIO_28_OUTPUT_VALUE & 0x1) << (31-28))	\
+     | ((PP_HWID_##hwid##_GPIO_29_OUTPUT_VALUE & 0x1) << (31-29))	\
+     | ((PP_HWID_##hwid##_GPIO_30_OUTPUT_VALUE & 0x1) << (31-30))	\
+     | ((PP_HWID_##hwid##_GPIO_31_OUTPUT_VALUE & 0x1) << (31-31)))
+#else
+# define _PP_GPIO0_OR_405EP_EXT(hwid) 0x0
+#endif
+
+/*
+ * Get the PLLMR(0|1) configuration register values
+ * for a given hardware id.
+ */
+#define PP_PLLMR0_DEFAULT(hwid) _PP_PLLMR0_DEFAULT(hwid)
+#define _PP_PLLMR0_DEFAULT(hwid) __PP_PLLMR0_DEFAULT(hwid)
+#define __PP_PLLMR0_DEFAULT(hwid)		\
+    PP_HWID_##hwid##_PLLMR0_DEFAULT
+#define PP_PLLMR1_DEFAULT(hwid) _PP_PLLMR1_DEFAULT(hwid)
+#define _PP_PLLMR1_DEFAULT(hwid) __PP_PLLMR1_DEFAULT(hwid)
+#define __PP_PLLMR1_DEFAULT(hwid)		\
+    PP_HWID_##hwid##_PLLMR1_DEFAULT
+
+#define PP_DYNAMIC_PLL(hwid) __PP_DYNAMIC_PLL(hwid)
+#define __PP_DYNAMIC_PLL(hwid)		\
+    PP_HWID_##hwid##_DYNAMIC_PLL
+
+# define PP_PLLMR0_SLOW(hwid) __PP_PLLMR0_SLOW(hwid)
+# define __PP_PLLMR0_SLOW(hwid)		\
+    PP_HWID_##hwid##_PLLMR0_SLOW
+# define PP_PLLMR1_SLOW(hwid) __PP_PLLMR1_SLOW(hwid)
+# define __PP_PLLMR1_SLOW(hwid)		\
+    PP_HWID_##hwid##_PLLMR1_DEFAULT
+# define PP_PLLMR0_FAST(hwid) __PP_PLLMR0_FAST(hwid)
+# define __PP_PLLMR0_FAST(hwid)		\
+    PP_HWID_##hwid##_PLLMR0_FAST
+# define PP_PLLMR1_FAST(hwid) __PP_PLLMR1_FAST(hwid)
+# define __PP_PLLMR1_FAST(hwid)		\
+    PP_HWID_##hwid##_PLLMR1_FAST
+
+/*
+ * Get the big physical memory area option for the kernel
+ * for a given hardware id.
+ *
+ * NOTES: - Hardware ids are always two characters wide - possibly
+ *	    with leading zeros.
+ *
+ *	  - The routine is wrapped more than once to stringify
+ *          the result of the actual macro expansion
+ */
+#define PP_BIGPHYSAREA_OPT(hwid)			\
+    PP_STRINGIFY_EXPANDED(__PP_BIGPHYSAREA_OPT(hwid))
+#define __PP_BIGPHYSAREA_OPT(hwid)			\
+    bigphysarea=PP_HWID_##hwid##_BIGPHYSAREA_PAGES
+
+/*
+ * Stringify a parameter (with or without macro expansion first).
+ */
+#define PP_STRINGIFY_EXPANDED(param) PP_STRINGIFY_UNEXPANDED(param)
+#define PP_STRINGIFY_UNEXPANDED(param) #param
+
+#endif /* _PEPPERCON_H */
Index: board/peppercon/strataflash.c
===================================================================
RCS file: board/peppercon/strataflash.c
diff -N board/peppercon/strataflash.c
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ board/peppercon/strataflash.c	3 Feb 2005 10:35:41 -0000	1.1
@@ -0,0 +1,795 @@
+/*
+ * (C) Copyright 2002
+ * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#undef  DEBUG_FLASH 
+/*
+ * This file implements a Common Flash Interface (CFI) driver for ppcboot.
+ * The width of the port and the width of the chips are determined at initialization.
+ * These widths are used to calculate the address for access CFI data structures.
+ * It has been tested on an Intel Strataflash implementation.
+ *
+ * References
+ * JEDEC Standard JESD68 - Common Flash Interface (CFI)
+ * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
+ * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
+ * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
+ *
+ * TODO
+ * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
+ * Add support for other command sets Use the PRI and ALT to determine command set
+ * Verify erase and program timeouts.
+ */
+
+#define FLASH_CMD_CFI			0x98
+#define FLASH_CMD_READ_ID		0x90
+#define FLASH_CMD_RESET			0xff
+#define FLASH_CMD_BLOCK_ERASE		0x20
+#define FLASH_CMD_ERASE_CONFIRM		0xD0
+#define FLASH_CMD_WRITE			0x40
+#define FLASH_CMD_PROTECT		0x60
+#define FLASH_CMD_PROTECT_SET		0x01
+#define FLASH_CMD_PROTECT_CLEAR		0xD0
+#define FLASH_CMD_CLEAR_STATUS		0x50
+#define FLASH_CMD_WRITE_TO_BUFFER       0xE8
+#define FLASH_CMD_WRITE_BUFFER_CONFIRM  0xD0
+
+#define FLASH_STATUS_DONE		0x80
+#define FLASH_STATUS_ESS		0x40
+#define FLASH_STATUS_ECLBS		0x20
+#define FLASH_STATUS_PSLBS		0x10
+#define FLASH_STATUS_VPENS		0x08
+#define FLASH_STATUS_PSS		0x04
+#define FLASH_STATUS_DPS		0x02
+#define FLASH_STATUS_R			0x01
+#define FLASH_STATUS_PROTECT		0x01
+
+#define FLASH_OFFSET_CFI		0x55
+#define FLASH_OFFSET_CFI_RESP		0x10
+#define FLASH_OFFSET_WTOUT		0x1F
+#define FLASH_OFFSET_WBTOUT             0x20
+#define FLASH_OFFSET_ETOUT		0x21
+#define FLASH_OFFSET_CETOUT             0x22
+#define FLASH_OFFSET_WMAX_TOUT		0x23
+#define FLASH_OFFSET_WBMAX_TOUT         0x24
+#define FLASH_OFFSET_EMAX_TOUT		0x25
+#define FLASH_OFFSET_CEMAX_TOUT         0x26
+#define FLASH_OFFSET_SIZE		0x27
+#define FLASH_OFFSET_INTERFACE          0x28
+#define FLASH_OFFSET_BUFFER_SIZE        0x2A
+#define FLASH_OFFSET_NUM_ERASE_REGIONS	0x2C
+#define FLASH_OFFSET_ERASE_REGIONS	0x2D
+#define FLASH_OFFSET_PROTECT		0x02
+#define FLASH_OFFSET_USER_PROTECTION    0x85
+#define FLASH_OFFSET_INTEL_PROTECTION   0x81
+
+
+#define FLASH_MAN_CFI			0x01000000
+
+
+
+
+typedef union {
+	unsigned char c;
+	unsigned short w;
+	unsigned long l;
+} cfiword_t;
+
+typedef union {
+	unsigned char * cp;
+	unsigned short *wp;
+	unsigned long *lp;
+} cfiptr_t;
+
+#define NUM_ERASE_REGIONS 4
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+
+
+static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c);
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf);
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_detect_cfi(flash_info_t * info);
+static ulong flash_get_size (ulong base, int banknum);
+static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword);
+static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt);
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len);
+#endif
+/*-----------------------------------------------------------------------
+ * create an address based on the offset and the port width
+ */
+inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset)
+{
+	return ((uchar *)(info->start[sect] + (offset * info->portwidth)));
+}
+/*-----------------------------------------------------------------------
+ * read a character at a port width address
+ */
+inline uchar flash_read_uchar(flash_info_t * info, uchar offset)
+{
+	uchar *cp;
+	cp = flash_make_addr(info, 0, offset);
+	return (cp[info->portwidth - 1]);
+}
+
+/*-----------------------------------------------------------------------
+ * read a short word by swapping for ppc format.
+ */
+ushort flash_read_ushort(flash_info_t * info, int sect,  uchar offset)
+{
+    uchar * addr;
+
+    addr = flash_make_addr(info, sect, offset);
+    return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ * read a long word by picking the least significant byte of each maiximum
+ * port size word. Swap for ppc format.
+ */
+ulong flash_read_long(flash_info_t * info, int sect,  uchar offset)
+{
+    uchar * addr;
+
+    addr = flash_make_addr(info, sect, offset);
+    return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) |
+	    (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size;
+	int i;
+	unsigned long  address;
+
+
+	/* The flash is positioned back to back, with the demultiplexing of the chip
+	 * based on the A24 address line.
+	 *
+	 */
+
+	address = CFG_FLASH_BASE;
+	size = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		size += flash_info[i].size = flash_get_size(address, i);
+		address += CFG_FLASH_INCREMENT;
+		if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i,
+				flash_info[0].size, flash_info[i].size<<20);
+		}
+	}
+
+	/* monitor protection ON by default */
+	flash_protect (FLAG_PROTECT_SET, CFG_MONITOR_BASE,
+		       CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+		       &flash_info[0]);
+
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int rcode = 0;
+	int prot;
+	int sect;
+
+	if( info->flash_id != FLASH_MAN_CFI) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+	if ((s_first < 0) || (s_first > s_last)) {
+		printf ("- no sectors to erase\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) { /* not protected */
+			flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
+			flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
+			flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
+			
+			if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) {
+				rcode = 1;
+			} else {
+				printf(".");
+			}
+				
+		}
+	}
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id != FLASH_MAN_CFI) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	printf("CFI conformant FLASH (%d x %d)",
+	       (info->portwidth	 << 3 ), (info->chipwidth  << 3 ));
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+	printf(" Erase timeout %ld ms, write timeout %ld ms\n",
+	       info->erase_blk_tout, info->write_tout);
+	printf(" Buffer write timeout %ld ms, buffer size %d\n",
+	       info->buffer_write_tout, info->buffer_size);
+      
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+#ifdef CFG_FLASH_EMPTY_INFO
+		int k;
+		int size;
+		int erased;
+		volatile unsigned long *flash;
+
+                /*
+                 * Check if whole sector is erased
+                 */
+                if (i != (info->sector_count-1))
+                  size = info->start[i+1] - info->start[i];
+                else
+                  size = info->start[0] + info->size - info->start[i];
+                erased = 1;
+                flash = (volatile unsigned long *)info->start[i];
+                size = size >> 2;        /* divide by 4 for longword access */
+                for (k=0; k<size; k++)
+                  {
+                    if (*flash++ != 0xffffffff)
+                      {
+                        erased = 0;
+                        break;
+                      }
+                  }
+
+		if ((i % 5) == 0)
+			printf ("\n   ");
+                /* print empty and read-only info */
+		printf (" %08lX%s%s",
+			info->start[i],
+			erased ? " E" : "  ",
+			info->protect[i] ? "RO " : "   ");
+#else
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+#endif
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong wp;
+	ulong cp;
+	int aln;
+	cfiword_t cword;
+	int i, rc;
+
+	/* get lower aligned address */
+	wp = (addr & ~(info->portwidth - 1));
+
+	/* handle unaligned start */
+	if((aln = addr - wp) != 0) {
+		cword.l = 0;
+		cp = wp;
+		for(i=0;i<aln; ++i, ++cp)
+			flash_add_byte(info, &cword, (*(uchar *)cp));
+
+		for(; (i< info->portwidth) && (cnt > 0) ; i++) {
+			flash_add_byte(info, &cword, *src++);
+			cnt--;
+			cp++;
+		}
+		for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
+			flash_add_byte(info, &cword, (*(uchar *)cp));
+		if((rc = flash_write_cfiword(info, wp, cword)) != 0)
+			return rc;
+		wp = cp;
+	}
+
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+	while(cnt >= info->portwidth) {
+		i = info->buffer_size > cnt? cnt: info->buffer_size;
+		if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK)
+			return rc;
+		wp += i;
+		src += i;
+		cnt -=i;
+	}
+#else
+	/* handle the aligned part */
+	while(cnt >= info->portwidth) {
+		cword.l = 0;
+		for(i = 0; i < info->portwidth; i++) {
+			flash_add_byte(info, &cword, *src++);
+		}
+		if((rc = flash_write_cfiword(info, wp, cword)) != 0)
+			return rc;
+		wp += info->portwidth;
+		cnt -= info->portwidth;
+	}
+#endif /* CFG_FLASH_USE_BUFFER_WRITE */
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	cword.l = 0;
+	for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) {
+		flash_add_byte(info, &cword, *src++);
+		--cnt;
+	}
+	for (; i<info->portwidth; ++i, ++cp) {
+		flash_add_byte(info, & cword, (*(uchar *)cp));
+	}
+
+	return flash_write_cfiword(info, wp, cword);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+	int retcode = 0;
+
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
+	if(prot)
+		flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
+	else
+		flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
+
+	if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout, 
+					 prot?"protect":"unprotect")) == 0) {
+
+		info->protect[sector] = prot;
+		/* Intel's unprotect unprotects all locking */
+		if(prot == 0) {
+			int i;
+			for(i = 0 ; i<info->sector_count; i++) {
+				if(info->protect[i])
+					flash_real_protect(info, i, 1);
+			}
+		}
+	}
+
+	return retcode;
+}
+/*-----------------------------------------------------------------------
+ *  wait for XSR.7 to be set. Time out with an error if it does not.
+ *  This routine does not set the flash to read-array mode.
+ */
+static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
+{
+	ulong start;
+
+	/* Wait for command completion */
+	start = get_timer (0);
+	while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
+		if (get_timer(start) > info->erase_blk_tout) {
+			printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]);
+			flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+			return ERR_TIMOUT;
+		}
+	}
+	return ERR_OK;
+}
+/*-----------------------------------------------------------------------
+ * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
+ * This routine sets the flash to read-array mode.
+ */
+static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
+{
+	int retcode;
+	retcode = flash_status_check(info, sector, tout, prompt);
+	if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) {
+		retcode = ERR_INVAL;
+		printf("Flash %s error at address %lx\n", prompt,info->start[sector]);
+		if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){
+			printf("Command Sequence Error.\n");
+		} else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){
+			printf("Block Erase Error.\n");
+		        retcode = ERR_NOT_ERASED;
+		} else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
+			printf("Locking Error\n");
+		}
+		if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){
+			printf("Block locked.\n");
+			retcode = ERR_PROTECTED;
+		}
+		if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
+			printf("Vpp Low Error.\n");
+	}
+	flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+	return retcode;
+}
+/*-----------------------------------------------------------------------
+ */
+static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c)
+{
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cword->c = c;
+		break;
+	case FLASH_CFI_16BIT:
+		cword->w = (cword->w << 8) | c;
+		break;
+	case FLASH_CFI_32BIT:
+		cword->l = (cword->l << 8) | c;
+	}
+}
+
+
+/*-----------------------------------------------------------------------
+ * make a proper sized command based on the port and chip widths
+ */
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf)
+{
+	int i;
+	uchar *cp = (uchar *)cmdbuf;
+	for(i=0; i< info->portwidth; i++)
+		*cp++ = ((i+1) % info->chipwidth) ? '\0':cmd;
+}
+
+/*
+ * Write a proper sized command to the correct address
+ */
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+
+	volatile cfiptr_t addr;
+	cfiword_t cword;
+	addr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		*addr.cp = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		*addr.wp = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		*addr.lp = cword.l;
+		break;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+	cptr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = (cptr.cp[0] == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		retval = (cptr.wp[0] == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		retval = (cptr.lp[0] == cword.l);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+/*-----------------------------------------------------------------------
+ */
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+	cptr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		retval = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		retval = ((cptr.lp[0] & cword.l) == cword.l);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+
+/*-----------------------------------------------------------------------
+ * detect if flash is compatible with the Common Flash Interface (CFI)
+ * http://www.jedec.org/download/search/jesd68.pdf
+ *
+*/
+static int flash_detect_cfi(flash_info_t * info)
+{
+
+	for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT;
+	    info->portwidth <<= 1) {
+		for(info->chipwidth =FLASH_CFI_BY8;
+		    info->chipwidth <= info->portwidth;
+		    info->chipwidth <<= 1) {
+			flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+			flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
+			if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') &&
+			   flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
+			   flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y'))
+				return 1;
+		}
+	}
+	return 0;
+}
+/*
+ * The following code cannot be run from FLASH!
+ *
+ */
+static ulong flash_get_size (ulong base, int banknum)
+{
+	flash_info_t * info = &flash_info[banknum];
+	int i, j;
+	int sect_cnt;
+	unsigned long sector;
+	unsigned long tmp;
+	int size_ratio;
+	uchar num_erase_regions;
+	int  erase_region_size;
+	int  erase_region_count;
+
+	info->start[0] = base;
+
+	if(flash_detect_cfi(info)){
+#ifdef DEBUG_FLASH
+		printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */
+#endif
+		size_ratio = info->portwidth / info->chipwidth;
+		num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
+#ifdef DEBUG_FLASH
+		printf("found %d erase regions\n", num_erase_regions);
+#endif
+		sect_cnt = 0;
+		sector = base;
+		for(i = 0 ; i < num_erase_regions; i++) {
+			if(i > NUM_ERASE_REGIONS) {
+				printf("%d erase regions found, only %d used\n",
+				       num_erase_regions, NUM_ERASE_REGIONS);
+				break;
+			}
+			tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS);
+			erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128;
+			tmp >>= 16;
+			erase_region_count = (tmp & 0xffff) +1;
+			for(j = 0; j< erase_region_count; j++) {
+				info->start[sect_cnt] = sector;
+				sector += (erase_region_size * size_ratio);
+				info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT);
+				sect_cnt++;
+			}
+		}
+
+		info->sector_count = sect_cnt;
+		/* multiply the size by the number of chips */
+		info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio;
+		info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
+		info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
+		info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
+		info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000;
+		info->flash_id = FLASH_MAN_CFI;
+	}
+
+	flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+	return(info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword)
+{
+
+	cfiptr_t ctladdr;
+	cfiptr_t cptr;
+	int flag;
+
+	ctladdr.cp = flash_make_addr(info, 0, 0);
+	cptr.cp = (uchar *)dest;
+
+
+	/* Check if Flash is (sufficiently) erased */
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		flag = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		flag = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		flag = ((cptr.lp[0] & cword.l)	== cword.l);
+		break;
+	default:
+		return 2;
+	}
+	if(!flag)
+		return 2;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
+
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cptr.cp[0] = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		cptr.wp[0] = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		cptr.lp[0] = cword.l;
+		break;
+	}
+
+	/* re-enable interrupts if necessary */
+	if(flag)
+		enable_interrupts();
+
+	return flash_full_status_check(info, 0, info->write_tout, "write");
+}
+
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+
+/* loop through the sectors from the highest address
+ * when the passed address is greater or equal to the sector address
+ * we have a match
+ */
+static int find_sector(flash_info_t *info, ulong addr)
+{
+	int sector;
+	for(sector = info->sector_count - 1; sector >= 0; sector--) {
+		if(addr >= info->start[sector]) 
+			break;
+	}
+	return sector;
+}
+
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len)
+{
+	
+	int sector;
+	int cnt;
+	int retcode;
+	volatile cfiptr_t src;
+	volatile cfiptr_t dst;
+
+	src.cp = cp;
+	dst.cp = (uchar *)dest;
+	sector = find_sector(info, dest);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
+	if((retcode = flash_status_check(info, sector, info->buffer_write_tout,
+					 "write to buffer")) == ERR_OK) {
+		switch(info->portwidth) {
+		case FLASH_CFI_8BIT:
+			cnt = len;
+			break;
+		case FLASH_CFI_16BIT:
+			cnt = len >> 1;
+			break;
+		case FLASH_CFI_32BIT:
+			cnt = len >> 2;
+			break;
+		default:
+			return ERR_INVAL;
+			break;
+		}
+		flash_write_cmd(info, sector, 0, (uchar)cnt-1);
+		while(cnt-- > 0) {
+			switch(info->portwidth) {
+			case FLASH_CFI_8BIT:
+				*dst.cp++ = *src.cp++;
+				break;
+			case FLASH_CFI_16BIT:
+				*dst.wp++ = *src.wp++;
+				break;
+			case FLASH_CFI_32BIT:
+				*dst.lp++ = *src.lp++;
+				break;
+			default:
+				return ERR_INVAL;
+				break;
+			}
+		}
+		flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM);
+		retcode = flash_full_status_check(info, sector, info->buffer_write_tout,
+					     "buffer write");
+	} else { 
+		flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); 
+		flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+	}
+ 
+	return retcode;
+}	
+#endif /* CFG_USE_FLASH_BUFFER_WRITE */
Index: board/peppercon/u-boot.lds
===================================================================
RCS file: board/peppercon/u-boot.lds
diff -N board/peppercon/u-boot.lds
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ board/peppercon/u-boot.lds	5 Apr 2005 14:17:06 -0000	1.2
@@ -0,0 +1,138 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR("/usr/powerpc-pp-linux-uclibc/lib");
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    /* protect this section from beeing removed by the linker (--gc-sections) */
+    KEEP(*(.resetvec))
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text .rel.text.*)		}
+  .rela.text     : { *(.rela.text .rela.text.*) 	}
+  .rel.data      : { *(.rel.data .rel.data.*)		}
+  .rela.data     : { *(.rela.data .rela.data.*) 	}
+  .rel.rodata    : { *(.rel.rodata .rel.rodata.*) 	}
+  .rela.rodata   : { *(.rela.rodata .rela.rodata.*) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt 		 : { *(.plt) }
+  .text      :
+  {
+    cpu/ppc4xx/start.o	(.text .text.*)
+    KEEP(common/environment.o(.text .text.*))
+
+    *(.text .text.*)
+    KEEP(*(.fixup))
+    KEEP(*(.got1))
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata .rodata.*)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { KEEP(*(.fini))    } =0
+  .ctors     : { KEEP(*(.ctors))   }
+  .dtors     : { KEEP(*(.dtors))   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got)) 
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data .data.*)
+    *(.data1)
+    *(.sdata .sdata.*)
+    *(.sdata2 .sdata2.*)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { KEEP(*(.u_boot_cmd)) }
+  __u_boot_cmd_end = .;
+
+  __start___ex_table = .;
+  __ex_table : { KEEP(*(__ex_table)) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss .sbss.*) *(.scommon)
+   *(.dynbss)
+   *(.bss .bss.*)
+   *(COMMON)
+  }
+  . = env_offset;
+  .ppcenv :
+  {
+    KEEP(common/environment.o(.ppcenv))
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
Index: common/Makefile
===================================================================
RCS file: /srv/CVS/pplinux/u-boot/common/Makefile,v
retrieving revision 1.1.333.1
retrieving revision 1.2
diff -u -r1.1.333.1 -r1.2
--- common/Makefile	3 Feb 2005 09:43:15 -0000	1.1.333.1
+++ common/Makefile	3 Feb 2005 10:35:41 -0000	1.2
@@ -40,6 +40,7 @@
 	  cmd_nand.o cmd_net.o cmd_nvedit.o \
 	  cmd_pci.o cmd_pcmcia.o cmd_portio.o \
 	  cmd_reginfo.o cmd_scsi.o cmd_spi.o cmd_usb.o cmd_vfd.o \
+	  cmd_config.o cmd_defaults.o cmd_develmode.o \
 	  command.o console.o devices.o dlmalloc.o docecc.o \
 	  environment.o env_common.o \
 	  env_flash.o env_eeprom.o env_nvram.o env_nowhere.o exports.o \
@@ -59,7 +60,7 @@
 	$(AR) crv $@ $(OBJS)
 
 environment.o: environment.c ../tools/envcrc
-	$(CC) $(AFLAGS) -Wa,--no-warn \
+	$(CC) $(CFLAGS) -Wa,--no-warn \
 		-DENV_CRC=$(shell ../tools/envcrc) \
 		-c -o $@ environment.c
 
Index: common/cmd_boot.c
===================================================================
RCS file: /srv/CVS/pplinux/u-boot/common/cmd_boot.c,v
retrieving revision 1.1.333.1
retrieving revision 1.2
diff -u -r1.1.333.1 -r1.2
--- common/cmd_boot.c	3 Feb 2005 09:43:15 -0000	1.1.333.1
+++ common/cmd_boot.c	3 Feb 2005 10:35:41 -0000	1.2
@@ -86,6 +86,6 @@
 
 U_BOOT_CMD(
 	reset, 1, 0,	do_reset,
-	"reset   - Perform RESET of the CPU\n",
+	"reset   - Perform RESET\n",
 	NULL
 );
Index: common/cmd_bootm.c
===================================================================
RCS file: /srv/CVS/pplinux/u-boot/common/cmd_bootm.c,v
retrieving revision 1.1.333.1
retrieving revision 1.2
diff -u -r1.1.333.1 -r1.2
--- common/cmd_bootm.c	3 Feb 2005 09:43:15 -0000	1.1.333.1
+++ common/cmd_bootm.c	3 Feb 2005 10:35:41 -0000	1.2
@@ -75,8 +75,10 @@
 
 int  gunzip (void *, int, unsigned char *, int *);
 
+#ifdef CONFIG_GZIP
 static void *zalloc(void *, unsigned, unsigned);
 static void zfree(void *, void *, unsigned);
+#endif
 
 #if (CONFIG_COMMANDS & CFG_CMD_IMI)
 static int image_info (unsigned long addr);
@@ -319,6 +321,7 @@
 #endif	/* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */
 		}
 		break;
+#ifdef CONFIG_GZIP
 	case IH_COMP_GZIP:
 		printf ("   Uncompressing %s ... ", name);
 		if (gunzip ((void *)ntohl(hdr->ih_load), unc_len,
@@ -328,6 +331,7 @@
 			do_reset (cmdtp, flag, argc, argv);
 		}
 		break;
+#endif /* CONFIG_GZIP */
 #ifdef CONFIG_BZIP2
 	case IH_COMP_BZIP2:
 		printf ("   Uncompressing %s ... ", name);
@@ -948,13 +952,16 @@
 }
 #endif
 
-
 #if (CONFIG_COMMANDS & CFG_CMD_BOOTD)
 int do_bootd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	int rcode = 0;
 #ifndef CFG_HUSH_PARSER
+# ifdef CONFIG_PEPPERCON
+	if (run_command (getenv ("bootcmd"), flag, 0) < 0) rcode = 1;
+# else
 	if (run_command (getenv ("bootcmd"), flag) < 0) rcode = 1;
+# endif
 #else
 	if (parse_string_outer(getenv("bootcmd"),
 		FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP) != 0 ) rcode = 1;
@@ -1192,6 +1199,8 @@
 	printf ("%s %s %s (%s)", arch, os, type, comp);
 }
 
+#ifdef CONFIG_GZIP
+
 #define	ZALLOC_ALIGNMENT	16
 
 static void *zalloc(void *x, unsigned items, unsigned size)
@@ -1273,6 +1282,7 @@
 
 	return (0);
 }
+#endif /* CONFIG_GZIP */
 
 #ifdef CONFIG_BZIP2
 void bz_internal_error(int errcode)
Index: common/cmd_config.c
===================================================================
RCS file: common/cmd_config.c
diff -N common/cmd_config.c
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ common/cmd_config.c	3 Feb 2005 10:35:41 -0000	1.1
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2001 William L. Pitts
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are freely
+ * permitted provided that the above copyright notice and this
+ * paragraph and the following disclaimer are duplicated in all
+ * such forms.
+ *
+ * This software is provided "AS IS" and without any express or
+ * implied warranties, including, without limitation, the implied
+ * warranties of merchantability and fitness for a particular
+ * purpose.
+ */
+
+#include <common.h>
+#include <command.h>
+
+
+#ifdef CONFIG_PEPPERCON
+
+static int do_config(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	gd_t * gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
+	printf("Please wait...\n");
+	gd->bd->bi_config_mode = 1;
+	gd->bd->bi_debug_mode = 0;
+	gd->serial_debug = 0;
+	return (run_command(getenv("bootcmd"), flag, 0) < 0 ? 1 : 0);
+}
+
+U_BOOT_CMD(
+        config, 1,              1,      do_config,
+        "config  - start configuration tool after bootup\n",
+	""
+);
+
+#endif	/* CONFIG_PEPPERCON */
Index: common/cmd_defaults.c
===================================================================
RCS file: common/cmd_defaults.c
diff -N common/cmd_defaults.c
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ common/cmd_defaults.c	24 May 2005 14:01:50 -0000	1.2
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2004 Peppercon AG
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are freely
+ * permitted provided that the above copyright notice and this
+ * paragraph and the following disclaimer are duplicated in all
+ * such forms.
+ *
+ * This software is provided "AS IS" and without any express or
+ * implied warranties, including, without limitation, the implied
+ * warranties of merchantability and fitness for a particular
+ * purpose.
+ */
+
+#include <common.h>
+#include <command.h>
+
+
+#ifdef CONFIG_PEPPERCON
+
+static int do_defaults(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	gd_t * gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
+	printf("Please wait...\n");
+	gd->bd->bi_def_jumper_set = PP_DEFAULTS_COMMAND;
+	gd->bd->bi_debug_mode = 0;
+	gd->serial_debug = 0;
+	return (run_command(getenv("bootcmd"), flag, 0) < 0 ? 1 : 0);
+}
+
+U_BOOT_CMD(
+	defaults, 1,              1,      do_defaults,
+        "defaults- set the device settings to their factory defaults\n",
+	""
+);
+
+#endif	/* CONFIG_PEPPERCON */
Index: common/cmd_develmode.c
===================================================================
RCS file: common/cmd_develmode.c
diff -N common/cmd_develmode.c
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ common/cmd_develmode.c	24 May 2005 14:01:50 -0000	1.2
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2004 Peppercon AG
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are freely
+ * permitted provided that the above copyright notice and this
+ * paragraph and the following disclaimer are duplicated in all
+ * such forms.
+ *
+ * This software is provided "AS IS" and without any express or
+ * implied warranties, including, without limitation, the implied
+ * warranties of merchantability and fitness for a particular
+ * purpose.
+ */
+
+#include <common.h>
+#include <command.h>
+
+
+#ifdef CONFIG_PEPPERCON
+
+static int do_devel_mode(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	gd_t * gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
+	gd->devel_mode = 1;
+	return 0;
+}
+
+U_BOOT_CMD(
+        erla, 1,              1,      do_devel_mode,
+        "",
+	""
+);
+
+#endif	/* CONFIG_PEPPERCON */
Index: common/cmd_net.c
===================================================================
RCS file: /srv/CVS/pplinux/u-boot/common/cmd_net.c,v
retrieving revision 1.1.333.1
retrieving revision 1.2
diff -u -r1.1.333.1 -r1.2
--- common/cmd_net.c	3 Feb 2005 09:43:15 -0000	1.1.333.1
+++ common/cmd_net.c	3 Feb 2005 10:35:41 -0000	1.2
@@ -40,11 +40,13 @@
 	return netboot_common (BOOTP, cmdtp, argc, argv);
 }
 
+#ifdef CONFIG_BOOTP 
 U_BOOT_CMD(
 	bootp,	3,	1,	do_bootp,
 	"bootp   - boot image via network using BootP/TFTP protocol\n",
 	"[loadAddress] [bootfilename]\n"
 );
+#endif
 
 int do_tftpb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
@@ -62,11 +64,13 @@
 	return netboot_common (RARP, cmdtp, argc, argv);
 }
 
+#if CONFIG_RARP
 U_BOOT_CMD(
 	rarpboot,	3,	1,	do_rarpb,
 	"rarpboot- boot image via network using RARP/TFTP protocol\n",
 	"[loadAddress] [bootfilename]\n"
 );
+#endif
 
 #if (CONFIG_COMMANDS & CFG_CMD_DHCP)
 int do_dhcp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
Index: common/command.c
===================================================================
RCS file: /srv/CVS/pplinux/u-boot/common/command.c,v
retrieving revision 1.1.333.1
retrieving revision 1.2
diff -u -r1.1.333.1 -r1.2
--- common/command.c	3 Feb 2005 09:43:15 -0000	1.1.333.1
+++ common/command.c	3 Feb 2005 10:35:41 -0000	1.2
@@ -80,7 +80,8 @@
  */
 int do_help (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
-	int i;
+	gd_t * gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
+	 int i;
 	int rcode = 0;
 
 	if (argc == 1) {	/*show list of commands */
@@ -122,7 +123,11 @@
 				return 1;
 			if (usage == NULL)
 				continue;
-			puts (usage);
+#ifdef CONFIG_PEPPERCON			
+			if (gd->devel_mode || cmd_array[i]->user_allowed)
+#endif
+			    puts (usage);
+			    
 		}
 		return 0;
 	}
@@ -143,7 +148,11 @@
 			}
 			putc ('\n');
 #else	/* no long help available */
+# ifdef CONFIG_PEPPERCON
+			if (cmdtp->usage && (gd->devel_mode || cmdtp->user_allowed))
+# else
 			if (cmdtp->usage)
+# endif
 				puts (cmdtp->usage);
 #endif	/* CFG_LONGHELP */
 		} else {
@@ -217,3 +226,11 @@
 
 	return NULL;	/* not found or ambiguous command */
 }
+
+#ifdef CONFIG_PEPPERCON
+void command_enable_user(const char *cmd)
+{
+	cmd_tbl_t* cmdtp = find_cmd(cmd);
+	if (cmdtp) cmdtp->user_allowed = 1;    
+}
+#endif
Index: common/env_common.c
===================================================================
RCS file: /srv/CVS/pplinux/u-boot/common/env_common.c,v
retrieving revision 1.1.333.1
retrieving revision 1.2
diff -u -r1.1.333.1 -r1.2
--- common/env_common.c	3 Feb 2005 09:43:15 -0000	1.1.333.1
+++ common/env_common.c	3 Feb 2005 10:35:41 -0000	1.2
@@ -208,6 +208,14 @@
 #endif
 
 #ifdef ENV_IS_EMBEDDED
+
+#ifdef CONFIG_PEPPERCON
+	/*
+	 * Environment is in separate section -> relocate it
+	 */
+	memcpy((void *)((ulong)env_ptr + gd->reloc_off), env_ptr, CFG_ENV_SIZE);
+#endif /* CONFIG_PEPPERCON */
+
 	/*
 	 * The environment buffer is embedded with the text segment,
 	 * just relocate the environment pointer
Index: common/environment.c
===================================================================
RCS file: /srv/CVS/pplinux/u-boot/common/environment.c,v
retrieving revision 1.1.333.1
retrieving revision 1.2
diff -u -r1.1.333.1 -r1.2
--- common/environment.c	3 Feb 2005 09:43:15 -0000	1.1.333.1
+++ common/environment.c	3 Feb 2005 10:35:41 -0000	1.2
@@ -50,6 +50,7 @@
      defined(CONFIG_FADS)	|| \
      defined(CONFIG_HYMOD)	|| \
      defined(CONFIG_ICU862)	|| \
+     defined(CONFIG_PEPPERCON)	|| \
      defined(CONFIG_R360MPI)	|| \
      defined(CONFIG_TQM8xxL)	|| \
      defined(CONFIG_RRVISION)	|| \
@@ -197,6 +198,6 @@
 /*
  * Add in absolutes.
  */
-GEN_ABS(env_offset, CFG_ENV_OFFSET);
+GEN_ABS(env_offset, CFG_ENV_ADDR);
 
 #endif /* ENV_IS_EMBEDDED */
Index: common/main.c
===================================================================
RCS file: /srv/CVS/pplinux/u-boot/common/main.c,v
retrieving revision 1.1.333.1
retrieving revision 1.2
diff -u -r1.1.333.1 -r1.2
--- common/main.c	3 Feb 2005 09:43:15 -0000	1.1.333.1
+++ common/main.c	3 Feb 2005 10:35:41 -0000	1.2
@@ -219,6 +219,10 @@
 static __inline__ int abortboot(int bootdelay)
 {
 	int abort = 0;
+#ifdef CONFIG_PEPPERCON
+	gd_t * gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
+	char ch;
+#endif
 
 #ifdef CONFIG_SILENT_CONSOLE
 	{
@@ -235,7 +239,11 @@
 #ifdef CONFIG_MENUPROMPT
 	printf(CONFIG_MENUPROMPT, bootdelay);
 #else
+# ifdef CONFIG_PEPPERCON
+	printf("Press ESC to stop autoboot: %2d ", bootdelay);
+# else
 	printf("Hit any key to stop autoboot: %2d ", bootdelay);
+# endif
 #endif
 
 #if defined CONFIG_ZERO_BOOTDELAY_CHECK
@@ -245,12 +253,22 @@
 	 */
 	if (bootdelay >= 0) {
 		if (tstc()) {	/* we got a key press	*/
+#ifdef CONFIG_PEPPERCON
+		        ch = getc();    /* get the incoming char */
+			if (ch == 0x1b) {
+			    abort  = 1;    /* don't auto boot */
+			    gd->serial_debug = 1;
+			    gd->bd->bi_debug_mode = 1;
+			    break;
+			}
+#else /* !CONFIG_PEPPERCON */
 			(void) getc();  /* consume input	*/
 			printf ("\b\b\b 0");
 			abort = 1; 	/* don't auto boot	*/
+#endif /* !CONFIG_PEPPERCON */
 		}
 	}
-#endif
+#endif /* CONFIG_ZERO_BOOTDELAY_CHECK */
 
 	while ((bootdelay > 0) && (!abort)) {
 		int i;
@@ -259,6 +277,16 @@
 		/* delay 100 * 10ms */
 		for (i=0; !abort && i<100; ++i) {
 			if (tstc()) {	/* we got a key press	*/
+#ifdef CONFIG_PEPPERCON
+			        ch = getc();    /* get the incoming char */
+				if (ch == 0x1b) {
+				    abort  = 1;    /* don't auto boot */
+				    bootdelay = 0; /* no more delay   */ 
+				    gd->serial_debug = 1;
+				    gd->bd->bi_debug_mode = 1;
+				    break;
+				}
+#else /* !CONFIG_PEPPERCON */
 				abort  = 1;	/* don't auto boot	*/
 				bootdelay = 0;	/* no more delay	*/
 # ifdef CONFIG_MENUKEY
@@ -267,6 +295,7 @@
 				(void) getc();  /* consume input	*/
 # endif
 				break;
+#endif /* !CONFIG_PEPPERCON */
 			}
 			udelay (10000);
 		}
@@ -412,7 +441,11 @@
 # endif
 
 # ifndef CFG_HUSH_PARSER
+#  ifdef CONFIG_PEPPERCON
+		run_command (s, 0, 0);
+#  else
 		run_command (s, 0);
+#  endif
 # else
 		parse_string_outer(s, FLAG_PARSE_SEMICOLON |
 				    FLAG_EXIT_FROM_LOOP);
@@ -428,7 +461,11 @@
 	    s = getenv("menucmd");
 	    if (s) {
 # ifndef CFG_HUSH_PARSER
-		run_command (s, bd, 0);
+#  ifdef CONFIG_PEPPERCON
+		run_command (s, 0, 0);
+#  else
+		run_command (s, 0);
+#  endif
 # else
 		parse_string_outer(s, FLAG_PARSE_SEMICOLON |
 				    FLAG_EXIT_FROM_LOOP);
@@ -486,7 +523,11 @@
 		if (len == -1)
 			printf ("<INTERRUPT>\n");
 		else
+#ifdef CONFIG_PEPPERCON
+			rc = run_command (lastcommand, flag, 1);
+#else
 			rc = run_command (lastcommand, flag);
+#endif
 
 		if (rc <= 0) {
 			/* invalid command or not repeatable, forget it */
@@ -574,6 +615,12 @@
 			puts ("\r\n");
 			return (p - console_buffer);
 
+#ifdef CONFIG_PEPPERCON
+		case 0x1B:
+		        /* do nothing on escape */
+		        break;
+#endif /* CONFIG_PEPPERCON */
+
 		case 0x03:				/* ^C - break		*/
 			console_buffer[0] = '\0';	/* discard input */
 			return (-1);
@@ -827,8 +874,15 @@
  * creates or modifies environment variables (like "bootp" does).
  */
 
+#ifdef CONFIG_PEPPERCON
+int run_command (const char *cmd, int flag, int interactive)
+#else
 int run_command (const char *cmd, int flag)
+#endif
 {
+#ifdef CONFIG_PEPPERCON
+	gd_t * gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
+#endif 
 	cmd_tbl_t *cmdtp;
 	char cmdbuf[CFG_CBSIZE];	/* working copy of cmd		*/
 	char *token;			/* start of token in cmdbuf	*/
@@ -913,6 +967,9 @@
 
 		/* found - check max args */
 		if (argc > cmdtp->maxargs) {
+#ifdef CONFIG_PEPPERCON
+		    if (!interactive || gd->devel_mode || cmdtp->user_allowed)
+#endif
 			printf ("Usage:\n%s\n", cmdtp->usage);
 			rc = -1;
 			continue;
@@ -935,9 +992,20 @@
 #endif	/* CFG_CMD_BOOTD */
 
 		/* OK - call function to do the command */
+#ifdef CONFIG_PEPPERCON
+		if (!interactive || gd->devel_mode || cmdtp->user_allowed) {
+		    if ((cmdtp->cmd) (cmdtp, flag, argc, argv) != 0) {
+			rc = -1;
+		    }
+		} else {
+		    printf ("Unknown command '%s' - try 'help'\n", argv[0]);
+		    return -1;
+		}
+#else /* !CONFIG_PEPPERCON */
 		if ((cmdtp->cmd) (cmdtp, flag, argc, argv) != 0) {
 			rc = -1;
 		}
+#endif /* !CONFIG_PEPPERCON */
 
 		repeatable &= cmdtp->repeatable;
 
@@ -969,7 +1037,11 @@
 			return 1;
 		}
 #ifndef CFG_HUSH_PARSER
+# ifdef CONFIG_PEPPERCON
+		if (run_command (arg, flag, 0) == -1)
+# else
 		if (run_command (arg, flag) == -1)
+# endif
 			return 1;
 #else
 		if (parse_string_outer(arg,
Index: common/miiphyutil.c
===================================================================
RCS file: /srv/CVS/pplinux/u-boot/common/miiphyutil.c,v
retrieving revision 1.1.333.1
retrieving revision 1.2
diff -u -r1.1.333.1 -r1.2
--- common/miiphyutil.c	3 Feb 2005 09:43:15 -0000	1.1.333.1
+++ common/miiphyutil.c	3 Feb 2005 10:35:41 -0000	1.2
@@ -47,19 +47,15 @@
 		 unsigned char *model, unsigned char *rev)
 {
 	unsigned int reg = 0;
+	unsigned short tmp;
 
-	/*
-	 * Trick: we are reading two 16 registers into a 32 bit variable
-	 * so we do a 16 read into the high order bits of the variable (big
-	 * endian, you know), shift it down 16 bits, and the read the rest.
-	 */
-	if (miiphy_read (addr, PHY_PHYIDR2, (unsigned short *) &reg) != 0) {
+	if (miiphy_read (addr, PHY_PHYIDR2, &tmp) != 0) {
 #ifdef DEBUG
 		printf ("PHY ID register 2 read failed\n");
 #endif
 		return (-1);
 	}
-	reg >>= 16;
+	reg = tmp;
 
 #ifdef DEBUG
 	printf ("PHY_PHYIDR2 @ 0x%x = 0x%04x\n", addr, reg);
@@ -69,12 +65,13 @@
 		return (-1);
 	}
 
-	if (miiphy_read (addr, PHY_PHYIDR1, (unsigned short *) &reg) != 0) {
+	if (miiphy_read (addr, PHY_PHYIDR1, &tmp) != 0) {
 #ifdef DEBUG
 		printf ("PHY ID register 1 read failed\n");
 #endif
 		return (-1);
 	}
+	reg |= tmp << 16;
 #ifdef DEBUG
 	printf ("PHY_PHYIDR[1,2] @ 0x%x = 0x%08x\n", addr, reg);
 #endif
Index: cpu/ppc4xx/405gp_enet.c
===================================================================
RCS file: /srv/CVS/pplinux/u-boot/cpu/ppc4xx/405gp_enet.c,v
retrieving revision 1.1.333.1
retrieving revision 1.3
diff -u -r1.1.333.1 -r1.3
--- cpu/ppc4xx/405gp_enet.c	3 Feb 2005 09:43:12 -0000	1.1.333.1
+++ cpu/ppc4xx/405gp_enet.c	6 Apr 2005 12:44:07 -0000	1.3
@@ -159,7 +159,7 @@
 static int tx_u_index = 0;		/* Transmit User Queue Index */
 static int tx_run[NUM_TX_BUFF];	/* Transmit Running Queue */
 
-#undef INFO_405_ENET 1
+#undef INFO_405_ENET
 #ifdef INFO_405_ENET
 static int packetSent = 0;
 static int packetReceived = 0;
@@ -173,6 +173,13 @@
 static int is_receiving = 0;	/* sync with eth interrupt */
 static int print_speed = 1;	/* print speed message upon start */
 
+static int emac_num = 0;
+#ifdef CONFIG_PEPPERCON
+static unsigned long emac_base = EMAC0_BASE;
+#else
+static unsigned long emac_base = EMAC_BASE;
+#endif
+
 /*-----------------------------------------------------------------------------+
  * Prototypes and externals.
  *-----------------------------------------------------------------------------*/
@@ -195,7 +202,8 @@
 	};
 
 	/* EMAC RESET */
-	out32 (EMAC_M0, EMAC_M0_SRST);
+	out32 (EMAC0_M0, EMAC_M0_SRST);
+	out32 (EMAC1_M0, EMAC_M0_SRST);
 
 	print_speed = 1;		/* print speed message again next time */
 }
@@ -204,6 +212,9 @@
 static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 {
 	int i;
+	unsigned char phy_1_available = 0;
+	unsigned char phy_0_available = 0;
+	unsigned char phy_addr = 1;
 	unsigned long reg;
 	unsigned long msr;
 	unsigned long speed;
@@ -256,12 +267,40 @@
 #endif /* CONFIG_440 */
 
 	/* EMAC RESET */
-	out32 (EMAC_M0, EMAC_M0_SRST);
+	out32 (EMAC0_M0, EMAC_M0_SRST);
+	out32 (EMAC1_M0, EMAC_M0_SRST);
 
 	/* wait for PHY to complete auto negotiation */
 	reg_short = 0;
 #ifndef CONFIG_CS8952_PHY
-	miiphy_read (CONFIG_PHY_ADDR, PHY_BMSR, &reg_short);
+
+#if defined(CONFIG_PEPPERCON)
+	if (miiphy_read (1, PHY_BMSR, &reg_short) == 0 && reg_short != 0xffff) {
+	    phy_1_available = 1;
+	}
+
+	if (miiphy_read (0, PHY_BMSR, &reg_short) == 0 && reg_short != 0xffff) {
+	    phy_0_available = 1;
+	}
+
+	if (phy_1_available && phy_0_available) {
+	    phy_addr = CONFIG_PREF_PHY_ADDR;
+	    printf ("Two PHYs found - use PHY on %s interface.\n", CONFIG_PREF_PHY_ADDR ? "first" : "second");
+	} else if (phy_1_available) {
+	    phy_addr = 1;
+	    puts ("PHY on first interface found.\n");
+	} else if (phy_0_available) {
+	    phy_addr = 0;
+	    puts ("PHY on second interface found.\n");
+	} else {
+	    puts ("No PHY found!\n");
+	}
+	emac_num = phy_addr > 0 ? 0 : 1;
+	emac_base = emac_num ? EMAC1_BASE : EMAC0_BASE;
+#else
+	phy_addr = CONFIG_PHY_ADDR
+	miiphy_read (phy_addr, PHY_BMSR, &reg_short);
+#endif
 
 	/*
 	 * Wait if PHY is able of autonegotiation and autonegotiation is not complete
@@ -279,23 +318,42 @@
 				break;
 			}
 
+#if defined(CONFIG_PEPPERCON) && defined(PP_FEAT_USBPOWERED)
+			if ((i % 100) == 0) {
+			    toggle_led_state();
+			}
+#endif
+								
 			if ((i++ % 1000) == 0)
 				putc ('.');
 			udelay (1000);	/* 1 ms */
-			miiphy_read (CONFIG_PHY_ADDR, PHY_BMSR, &reg_short);
+			miiphy_read (phy_addr, PHY_BMSR, &reg_short);
 		}
 		puts (" done\n");
 		udelay (500000);	/* another 500 ms (results in faster booting) */
 	}
 #endif
-	speed = miiphy_speed (CONFIG_PHY_ADDR);
-	duplex = miiphy_duplex (CONFIG_PHY_ADDR);
+	speed = miiphy_speed (phy_addr);
+	duplex = miiphy_duplex (phy_addr);
 	if (print_speed) {
 		print_speed = 0;
 		printf ("ENET Speed is %d Mbps - %s duplex connection\n",
 			(int) speed, (duplex == HALF) ? "HALF" : "FULL");
 	}
 
+#ifdef CONFIG_PEPPERCON
+	/* clear the CRS Select bit - this solves problems with 10BaseT */
+	{
+		unsigned short data;
+		miiphy_read(phy_addr, 0x10, &data);
+		data &= ~0x80DD; // clear CRS Select and reserved bits
+		miiphy_write(phy_addr, 0x10, data);
+	}
+
+	/* set LED configuration */
+	miiphy_write(phy_addr, 0x14, PP_(PHY_LED_CFG_VALUE, PP_HWID));
+#endif
+
 	/* set the Mal configuration reg */
 #if defined(CONFIG_440)
 	/* Errata 1.12: MAL_1 -- Disable MAL bursting */
@@ -383,20 +441,37 @@
 
 	out32 (EMAC_IAL, reg);
 
-	/* setup MAL tx & rx channel pointers */
-	mtdcr (maltxctp0r, tx);
-	mtdcr (malrxctp0r, rx);
-
-	/* Reset transmit and receive channels */
-	mtdcr (malrxcarr, 0x80000000);	/* 2 channels */
-	mtdcr (maltxcarr, 0x80000000);	/* 2 channels */
-
-	/* Enable MAL transmit and receive channels */
-	mtdcr (maltxcasr, 0x80000000);	/* 1 channel */
-	mtdcr (malrxcasr, 0x80000000);	/* 1 channel */
+	if (emac_num == 1) {
+	    /* setup MAL tx & rx channel pointers */
+	    mtdcr (maltxctp0r_1, tx);
+	    mtdcr (malrxctp0r_1, rx);
+
+	    /* Reset transmit and receive channels */
+	    mtdcr (malrxcarr, 0x40000000);	/* 2 channels */
+	    mtdcr (maltxcarr, 0x20000000);	/* 2 channels */
+
+	    /* Enable MAL transmit and receive channels */
+	    mtdcr (maltxcasr, 0x20000000);	/* 1 channel */
+	    mtdcr (malrxcasr, 0x40000000);	/* 1 channel */
 
-	/* set RX buffer size */
-	mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
+	    /* set RX buffer size */
+	    mtdcr (malrcbs0_1, ENET_MAX_MTU_ALIGNED / 16);
+	} else {
+	    /* setup MAL tx & rx channel pointers */
+	    mtdcr (maltxctp0r_0, tx);
+	    mtdcr (malrxctp0r_0, rx);
+
+	    /* Reset transmit and receive channels */
+	    mtdcr (malrxcarr, 0x80000000);	/* 2 channels */
+	    mtdcr (maltxcarr, 0x80000000);	/* 2 channels */
+
+	    /* Enable MAL transmit and receive channels */
+	    mtdcr (maltxcasr, 0x80000000);	/* 1 channel */
+	    mtdcr (malrxcasr, 0x80000000);	/* 1 channel */
+
+	    /* set RX buffer size */
+	    mtdcr (malrcbs0_0, ENET_MAX_MTU_ALIGNED / 16);
+	}
 
 	/* set transmit enable & receive enable */
 	out32 (EMAC_M0, EMAC_M0_TXE | EMAC_M0_RXE);
@@ -434,7 +509,7 @@
 #endif /* CONFIG_440 */
 
 	/* Frame gap set */
-	out32 (EMAC_I_FRAME_GAP_REG, 0x00000008);
+	out32 (EMAC_I_FRAME_GAP_REG, 0x00000004);
 
 	if (first_init == 0) {
 		/*
@@ -675,7 +750,7 @@
 		/* check for EOB on valid channels            */
 		if ((my_uicmsr & UIC_MAL_RXEOB) != 0) {
 			mal_rx_eob = mfdcr (malrxeobisr);
-			if ((mal_rx_eob & 0x80000000) != 0) {	/* call emac routine for channel 0 */
+			if ((mal_rx_eob & (emac_num == 1 ? 0x40000000 : 0x80000000)) != 0) {	/* call emac routine for channel 0 */
 				/* clear EOB
 				   mtdcr(malrxeobisr, mal_rx_eob); */
 				enet_rcv (emac_isr);
@@ -743,7 +818,7 @@
 	int loop_count = 0;
 
 	rx_eob_isr = mfdcr (malrxeobisr);
-	if ((0x80000000 >> (EMAC_RXCHL - 1)) & rx_eob_isr) {
+	if (((emac_num == 1 ? 0x40000000 : 0x80000000) >> (EMAC_RXCHL - 1)) & rx_eob_isr) {
 		/* clear EOB */
 		mtdcr (malrxeobisr, rx_eob_isr);
 
Index: cpu/ppc4xx/405gp_pci.c
===================================================================
RCS file: /srv/CVS/pplinux/u-boot/cpu/ppc4xx/405gp_pci.c,v
retrieving revision 1.1.333.1
retrieving revision 1.2
diff -u -r1.1.333.1 -r1.2
--- cpu/ppc4xx/405gp_pci.c	3 Feb 2005 09:43:12 -0000	1.1.333.1
+++ cpu/ppc4xx/405gp_pci.c	3 Feb 2005 10:35:41 -0000	1.2
@@ -92,7 +92,7 @@
 
 	int i, reg_num = 0;
 	bd_t *bd = gd->bd;
-
+	unsigned short data16;
 	unsigned short temp_short;
 	unsigned long ptmpcila[2] = {CFG_PCI_PTM1PCI, CFG_PCI_PTM2PCI};
 #if defined(CONFIG_CPCI405)
@@ -102,7 +102,20 @@
 	unsigned long ptmla[2]    = {CFG_PCI_PTM1LA, CFG_PCI_PTM2LA};
 	unsigned long ptmms[2]    = {CFG_PCI_PTM1MS, CFG_PCI_PTM2MS};
 #endif
-#if defined(CONFIG_PIP405) || defined (CONFIG_MIP405)
+#if defined(CONFIG_PEPPERCON)
+	unsigned long pmmla[3]    = {
+		CFG_PCI_PMM0LA, CFG_PCI_PMM1LA, CFG_PCI_PMM2LA
+	};
+	unsigned long pmmma[3]    = {
+		CFG_PCI_PMM0MA, CFG_PCI_PMM1MA, CFG_PCI_PMM2MA
+	};
+	unsigned long pmmpcila[3] = {
+		CFG_PCI_PMM0PCILA, CFG_PCI_PMM1PCILA, CFG_PCI_PMM2PCILA
+	};
+	unsigned long pmmpciha[3] = {
+		CFG_PCI_PMM0PCIHA, CFG_PCI_PMM1PCIHA, CFG_PCI_PMM2PCIHA
+	};
+#elif defined(CONFIG_PIP405) || defined (CONFIG_MIP405)
 	unsigned long pmmla[3]    = {0x80000000, 0xA0000000, 0};
 	unsigned long pmmma[3]    = {0xE0000001, 0xE0000001, 0};
 	unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0};
@@ -120,6 +133,9 @@
 	hose->first_busno = 0;
 	hose->last_busno = 0xff;
 
+#ifdef CONFIG_PEPPERCON
+	reg_num = 0;
+#else
 	/* ISA/PCI I/O space */
 	pci_set_region(hose->regions + reg_num++,
 		       MIN_PCI_PCI_IOADDR,
@@ -135,6 +151,7 @@
 		       PCI_REGION_IO);
 
 	reg_num = 2;
+#endif
 
 	/* Memory spaces */
 	for (i=0; i<2; i++)
@@ -170,6 +187,18 @@
 
 	pci_register_hose(hose);
 
+#ifdef CONFIG_PEPPERCON
+	/* this resets the PCI bus, which is necessary for the WLAN mini pci card,
+	   which didn't worked after rebooting */
+	pci_read_config_word(PCIDEVID_405GP, 0x60, &data16);
+	pci_write_config_word(PCIDEVID_405GP, 0x60, data16 | 0x1000);
+	
+	udelay(1000); /* is PCI spec 2.1: 4.2.3.2 applicable here? */
+	
+	pci_read_config_word(PCIDEVID_405GP, 0x60, &data16);
+	pci_write_config_word(PCIDEVID_405GP, 0x60, data16 & ~0x1000);
+#endif
+	
 	/*--------------------------------------------------------------------------+
 	 * 405GP PCI Master configuration.
 	 * Map one 512 MB range of PLB/processor addresses to PCI memory space.
@@ -368,12 +397,13 @@
 	{CFG_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST,
 	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge},
 #endif
+#ifndef CONFIG_PEPPERCON
 	{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA,
 	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
 
 	{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA,
 	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
-
+#endif
 	{ }
 };
 
Index: cpu/ppc4xx/cpu_init.c
===================================================================
RCS file: /srv/CVS/pplinux/u-boot/cpu/ppc4xx/cpu_init.c,v
retrieving revision 1.1.333.1
retrieving revision 1.3
diff -u -r1.1.333.1 -r1.3
--- cpu/ppc4xx/cpu_init.c	3 Feb 2005 09:43:12 -0000	1.1.333.1
+++ cpu/ppc4xx/cpu_init.c	6 Apr 2005 12:44:07 -0000	1.3
@@ -184,6 +184,10 @@
 	mtebc(pb7cr, CFG_EBC_PB7CR);
 #endif
 
+#if (defined(CFG_EBC_EPCR))
+	mtebc(epcr, CFG_EBC_EPCR);
+#endif
+     
 #if defined(CONFIG_WATCHDOG)
 	unsigned long val;
 
@@ -238,7 +242,8 @@
 	reg |= bd->bi_enetaddr[0];           /* set high address */
 	reg = reg << 8;
 	reg |= bd->bi_enetaddr[1];
-	out32 (EMAC_IAH, reg);
+	out32 (EMAC0_IAH, reg);
+	out32 (EMAC1_IAH, reg);
 
 	reg = 0x00000000;
 	reg |= bd->bi_enetaddr[2];           /* set low address  */
@@ -248,7 +253,8 @@
 	reg |= bd->bi_enetaddr[4];
 	reg = reg << 8;
 	reg |= bd->bi_enetaddr[5];
-	out32 (EMAC_IAL, reg);
+	out32 (EMAC0_IAL, reg);
+	out32 (EMAC1_IAL, reg);
 
 #if defined(CONFIG_405GP)
 	/*
Index: cpu/ppc4xx/interrupts.c
===================================================================
RCS file: /srv/CVS/pplinux/u-boot/cpu/ppc4xx/interrupts.c,v
retrieving revision 1.1.333.1
retrieving revision 1.2
diff -u -r1.1.333.1 -r1.2
--- cpu/ppc4xx/interrupts.c	3 Feb 2005 09:43:12 -0000	1.1.333.1
+++ cpu/ppc4xx/interrupts.c	3 Feb 2005 10:35:41 -0000	1.2
@@ -375,8 +375,15 @@
 #if 0
 	printf ("*** Timer Interrupt *** ");
 #endif
+
 	timestamp++;
 
+#if defined(CONFIG_PEPPERCON) && defined(PP_FEAT_USBPOWERED)
+	if ((timestamp % 100) == 0) {
+	    toggle_led_state();
+	}
+#endif
+	
 #if defined(CONFIG_WATCHDOG)
 	if ((timestamp % 1000) == 0)
 		reset_4xx_watchdog();
Index: cpu/ppc4xx/miiphy.c
===================================================================
RCS file: /srv/CVS/pplinux/u-boot/cpu/ppc4xx/miiphy.c,v
retrieving revision 1.1.333.1
retrieving revision 1.3
diff -u -r1.1.333.1 -r1.3
--- cpu/ppc4xx/miiphy.c	3 Feb 2005 09:43:12 -0000	1.1.333.1
+++ cpu/ppc4xx/miiphy.c	6 Apr 2005 12:44:07 -0000	1.3
@@ -107,9 +107,6 @@
 	sta_reg = sta_reg | (addr << 5);	/* Phy address */
 
 	out32 (EMAC_STACR, sta_reg);
-#if 0	/* test-only */
-	printf ("a2: write: EMAC_STACR=0x%0x\n", sta_reg);	/* test-only */
-#endif
 
 	sta_reg = in32 (EMAC_STACR);
 	i = 0;
@@ -123,13 +120,15 @@
 		sta_reg = in32 (EMAC_STACR);
 	}
 	if ((sta_reg & EMAC_STACR_PHYE) != 0) {
+#if 0
 		printf ("read err 3\n");
 		printf ("a2: read: EMAC_STACR=0x%0lx, i=%d\n",
 			sta_reg, (int) i);	/* test-only */
+#endif
 		return -1;
 	}
 
-	*value = *(short *) (&sta_reg);
+	memcpy (value, &sta_reg, 2);   /* read data */
 	return 0;
 
 
Index: cpu/ppc4xx/serial.c
===================================================================
RCS file: /srv/CVS/pplinux/u-boot/cpu/ppc4xx/serial.c,v
retrieving revision 1.1.333.1
retrieving revision 1.2
diff -u -r1.1.333.1 -r1.2
--- cpu/ppc4xx/serial.c	3 Feb 2005 09:43:12 -0000	1.1.333.1
+++ cpu/ppc4xx/serial.c	3 Feb 2005 10:35:41 -0000	1.2
@@ -543,7 +543,23 @@
 void serial_putc (const char c)
 {
 	int i;
+#ifdef CONFIG_PEPPERCON
+	gd_t * gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
 
+	/* only if we have a e-RIC debug cable attached and debugging is enabled */
+	if (gd->serial_debug) {
+		if (c == '\n')
+			serial_putc ('\r');
+
+		/* check THRE bit, wait for transmiter available */
+		for (i = 1; i < 3500; i++) {
+		    if ((in8 (ACTING_UART0_BASE + UART_LSR) & 0x20) == 0x20)
+			break;
+		    udelay (100);
+		}
+		out8 (ACTING_UART0_BASE + UART_THR, c);	/* put character out */
+	}
+#else /* !CONFIG_PEPPERCON */
 	if (c == '\n')
 		serial_putc ('\r');
 
@@ -554,6 +570,7 @@
 		udelay (100);
 	}
 	out8 (ACTING_UART0_BASE + UART_THR, c);	/* put character out */
+#endif /* !CONFIG_PEPPERCON */
 }
 
 
@@ -569,50 +586,110 @@
 {
 	unsigned char status = 0;
 
-	while (1) {
+#ifdef CONFIG_PEPPERCON
+	gd_t * gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
+
+	/* only if we have a e-RIC debug cable attached */
+	if (gd->debug_cable_present) {
+#endif /* CONFIG_PEPPERCON */
+		while (1) {
 #if defined(CONFIG_HW_WATCHDOG)
-		WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
+			WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
 #endif	/* CONFIG_HW_WATCHDOG */
+			status = in8 (ACTING_UART0_BASE + UART_LSR);
+			if ((status & asyncLSRDataReady1) != 0x0) {
+				break;
+			}
+			if ((status & ( asyncLSRFramingError1 |
+					asyncLSROverrunError1 |
+					asyncLSRParityError1  |
+					asyncLSRBreakInterrupt1 )) != 0) {
+				out8 (ACTING_UART0_BASE + UART_LSR,
+				      asyncLSRFramingError1 |
+				      asyncLSROverrunError1 |
+				      asyncLSRParityError1  |
+				      asyncLSRBreakInterrupt1);
+			}
+		}
+		return (0x000000ff & (int) in8 (ACTING_UART0_BASE));
+#ifdef CONFIG_PEPPERCON
+	}
+	return 0;
+#endif /* CONFIG_PEPPERCON */
+}
+
+
+int serial_tstc ()
+{
+	unsigned char status;
+#ifdef CONFIG_PEPPERCON
+	gd_t * gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
+
+	/* only if we have a e-RIC debug cable attached */
+	if (gd->debug_cable_present) {
+#endif /* CONFIG_PEPPERCON */
 		status = in8 (ACTING_UART0_BASE + UART_LSR);
 		if ((status & asyncLSRDataReady1) != 0x0) {
-			break;
+			return (1);
 		}
 		if ((status & ( asyncLSRFramingError1 |
 				asyncLSROverrunError1 |
 				asyncLSRParityError1  |
 				asyncLSRBreakInterrupt1 )) != 0) {
-			out8 (ACTING_UART0_BASE + UART_LSR,
-			      asyncLSRFramingError1 |
-			      asyncLSROverrunError1 |
-			      asyncLSRParityError1  |
-			      asyncLSRBreakInterrupt1);
+		    out8 (ACTING_UART0_BASE + UART_LSR,
+			  asyncLSRFramingError1 |
+			  asyncLSROverrunError1 |
+			  asyncLSRParityError1  |
+			  asyncLSRBreakInterrupt1);
 		}
+#ifdef CONFIG_PEPPERCON
 	}
-	return (0x000000ff & (int) in8 (ACTING_UART0_BASE));
+#endif /* CONFIG_PEPPERCON */
+	return 0;
 }
 
-
-int serial_tstc ()
+#ifdef CONFIG_PEPPERCON
+int serial_debug_cable_present(void)
 {
-	unsigned char status;
-
-	status = in8 (ACTING_UART0_BASE + UART_LSR);
-	if ((status & asyncLSRDataReady1) != 0x0) {
-		return (1);
-	}
-	if ((status & ( asyncLSRFramingError1 |
-			asyncLSROverrunError1 |
-			asyncLSRParityError1  |
-			asyncLSRBreakInterrupt1 )) != 0) {
-		out8 (ACTING_UART0_BASE + UART_LSR,
-		      asyncLSRFramingError1 |
-		      asyncLSROverrunError1 |
-		      asyncLSRParityError1  |
-		      asyncLSRBreakInterrupt1);
+#define TOGGLE_COUNT 20
+	int dcd_toggle_count = 0;
+	int cts_toggle_count = 0;
+	u8 mcr = 0;
+	u8 mcr_save = 0;
+	u8 msr;
+	int i;
+
+	int re_enable = disable_interrupts();
+
+	mcr_save = in8(ACTING_UART0_BASE + UART_MCR);
+	out8(ACTING_UART0_BASE + UART_MCR, mcr);  /* set DTR & RTS to 0 */
+	msr = in8(ACTING_UART0_BASE + UART_MSR);
+	/*
+	 * NOTE: Settimg DTR and RTS at the same time will not give the expected
+	 *       result. So we test it sequentially.
+	 */
+	for (i = 0; i < TOGGLE_COUNT; i++) { /* check DTR and DCD connection */
+		mcr = (~mcr) & 0x1;
+		out8(ACTING_UART0_BASE + UART_MCR, mcr);
+		udelay(10000);
+		msr = in8(ACTING_UART0_BASE + UART_MSR);
+		dcd_toggle_count += (msr & 0x8) >> 3;
+	}
+	for (i = 0; i < TOGGLE_COUNT; i++) { /* check RTS and CTS connection */
+		mcr = (~mcr) & 0x2;
+		out8(ACTING_UART0_BASE + UART_MCR, mcr);
+		udelay(10000);
+		msr = in8(ACTING_UART0_BASE + UART_MSR);
+		cts_toggle_count += msr & 0x1;
 	}
-	return 0;
-}
+	out8(ACTING_UART0_BASE + UART_MCR, mcr_save);  /* restore UART MCR register */
+
+	if (re_enable) enable_interrupts();
 
+	return (dcd_toggle_count == TOGGLE_COUNT ||
+		cts_toggle_count == TOGGLE_COUNT);
+}
+#endif /* CONFIG_PEPPERCON */
 
 #if CONFIG_SERIAL_SOFTWARE_FIFO
 
Index: cpu/ppc4xx/speed.c
===================================================================
RCS file: /srv/CVS/pplinux/u-boot/cpu/ppc4xx/speed.c,v
retrieving revision 1.1.333.1
retrieving revision 1.2
diff -u -r1.1.333.1 -r1.2
--- cpu/ppc4xx/speed.c	3 Feb 2005 09:43:12 -0000	1.1.333.1
+++ cpu/ppc4xx/speed.c	29 Apr 2005 08:43:29 -0000	1.2
@@ -189,6 +189,21 @@
 	return val;
 }
 
+/********************************************
+ * get_EPB_freq
+ * return EPB bus freq in Hz
+ *********************************************/
+ulong get_EPB_freq (void)
+{
+	ulong val = 0;
+
+	PPC405_SYS_INFO sys_info;
+
+	get_sys_info (&sys_info);
+	val = sys_info.freqPLB / sys_info.pllExtBusDiv;
+
+	return val;
+}
 
 /********************************************
  * get_PCI_freq
@@ -363,6 +378,21 @@
 	return val;
 }
 
+/********************************************
+ * get_EPB_freq
+ * return EPB bus freq in Hz
+ *********************************************/
+ulong get_EPB_freq (void)
+{
+	ulong val = 0;
+
+	PPC405_SYS_INFO sys_info;
+
+	get_sys_info (&sys_info);
+	val = sys_info.freqPLB / sys_info.pllExtBusDiv;
+
+	return val;
+}
 
 /********************************************
  * get_PCI_freq
Index: doc/nios2_diff_readme.txt
===================================================================
RCS file: doc/nios2_diff_readme.txt
diff -N doc/nios2_diff_readme.txt
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ doc/nios2_diff_readme.txt	29 Apr 2005 08:43:29 -0000	1.1
@@ -0,0 +1,7 @@
+The file 'nios2.diff' contains the first try to get NIOS2 support running
+in the U-Boot. It was taught to be used for the KIRA100 platform but we decided
+against it later. So its removed from the code and only available for reference
+or later use in this patch.
+
+The NIOS2 support was added in 'vsc2_branch', the patch was generated
+with a diff between 'vsc2_branch-point-20040901' and 'vsc2_branch-1st-merge-20050419'.
Index: include/405gp_enet.h
===================================================================
RCS file: /srv/CVS/pplinux/u-boot/include/405gp_enet.h,v
retrieving revision 1.1.333.1
retrieving revision 1.3
diff -u -r1.1.333.1 -r1.3
--- include/405gp_enet.h	3 Feb 2005 09:43:16 -0000	1.1.333.1
+++ include/405gp_enet.h	6 Apr 2005 12:44:07 -0000	1.3
@@ -78,35 +78,42 @@
 #if defined(CONFIG_440)
 #define EMAC_BASE 			(CFG_PERIPHERAL_BASE + 0x0800)
 #else
-#define EMAC_BASE 			0xEF600800
+# define EMAC0_BASE 		        0xEF600800
+# define EMAC1_BASE                     0xEF600900
 #endif
 
-#define EMAC_M0 			(EMAC_BASE)
-#define EMAC_M1 			(EMAC_BASE + 4)
-#define EMAC_TXM0				(EMAC_BASE + 8)
-#define EMAC_TXM1		 		(EMAC_BASE + 12)
-#define EMAC_RXM		 		(EMAC_BASE + 16)
-#define EMAC_ISR		 		(EMAC_BASE + 20)
-#define EMAC_IER		 		(EMAC_BASE + 24)
-#define EMAC_IAH		 		(EMAC_BASE + 28)
-#define EMAC_IAL		 		(EMAC_BASE + 32)
-#define EMAC_VLAN_TPID_REG 		(EMAC_BASE + 36)
-#define EMAC_VLAN_TCI_REG 		(EMAC_BASE + 40)
-#define EMAC_PAUSE_TIME_REG 		(EMAC_BASE + 44)
-#define EMAC_IND_HASH_1			(EMAC_BASE + 48)
-#define EMAC_IND_HASH_2			(EMAC_BASE + 52)
-#define EMAC_IND_HASH_3			(EMAC_BASE + 56)
-#define EMAC_IND_HASH_4			(EMAC_BASE + 60)
-#define EMAC_GRP_HASH_1			(EMAC_BASE + 64)
-#define EMAC_GRP_HASH_2			(EMAC_BASE + 68)
-#define EMAC_GRP_HASH_3			(EMAC_BASE + 72)
-#define EMAC_GRP_HASH_4			(EMAC_BASE + 76)
-#define EMAC_LST_SRC_LOW		(EMAC_BASE + 80)
-#define EMAC_LST_SRC_HI			(EMAC_BASE + 84)
-#define EMAC_I_FRAME_GAP_REG		(EMAC_BASE + 88)
-#define EMAC_STACR			(EMAC_BASE + 92)
-#define EMAC_TRTR				(EMAC_BASE + 96)
-#define EMAC_RX_HI_LO_WMARK		(EMAC_BASE + 100)
+#define EMAC0_M0 			(EMAC0_BASE)
+#define EMAC1_M0 			(EMAC1_BASE)
+#define EMAC_M0 			(emac_base)
+#define EMAC_M1 			(emac_base + 4)
+#define EMAC_TXM0			(emac_base + 8)
+#define EMAC_TXM1			(emac_base + 12)
+#define EMAC_RXM			(emac_base + 16)
+#define EMAC_ISR			(emac_base + 20)
+#define EMAC_IER			(emac_base + 24)
+#define EMAC_IAH			(emac_base + 28)
+#define EMAC_IAL			(emac_base + 32)
+#define EMAC0_IAH			(EMAC0_BASE + 28)
+#define EMAC0_IAL			(EMAC0_BASE + 32)
+#define EMAC1_IAH			(EMAC1_BASE + 28)
+#define EMAC1_IAL			(EMAC1_BASE + 32)
+#define EMAC_VLAN_TPID_REG 		(emac_base + 36)
+#define EMAC_VLAN_TCI_REG 		(emac_base + 40)
+#define EMAC_PAUSE_TIME_REG 		(emac_base + 44)
+#define EMAC_IND_HASH_1			(emac_base + 48)
+#define EMAC_IND_HASH_2			(emac_base + 52)
+#define EMAC_IND_HASH_3			(emac_base + 56)
+#define EMAC_IND_HASH_4			(emac_base + 60)
+#define EMAC_GRP_HASH_1			(emac_base + 64)
+#define EMAC_GRP_HASH_2			(emac_base + 68)
+#define EMAC_GRP_HASH_3			(emac_base + 72)
+#define EMAC_GRP_HASH_4			(emac_base + 76)
+#define EMAC_LST_SRC_LOW		(emac_base + 80)
+#define EMAC_LST_SRC_HI			(emac_base + 84)
+#define EMAC_I_FRAME_GAP_REG		(emac_base + 88)
+#define EMAC_STACR			(0xEF600800 + 92)
+#define EMAC_TRTR			(emac_base + 96)
+#define EMAC_RX_HI_LO_WMARK		(emac_base + 100)
 
 /* bit definitions */
 /* MODE REG 0 */
Index: include/command.h
===================================================================
RCS file: /srv/CVS/pplinux/u-boot/include/command.h,v
retrieving revision 1.1.333.1
retrieving revision 1.2
diff -u -r1.1.333.1 -r1.2
--- include/command.h	3 Feb 2005 09:43:16 -0000	1.1.333.1
+++ include/command.h	3 Feb 2005 10:35:41 -0000	1.2
@@ -46,6 +46,9 @@
 #ifdef	CFG_LONGHELP
 	char		*help;		/* Help  message	(long)	*/
 #endif
+#ifdef CONFIG_PEPPERCON
+	int		user_allowed;	/* allow execution also in user mode */
+#endif
 };
 
 typedef struct cmd_tbl_s	cmd_tbl_t;
@@ -57,6 +60,10 @@
 /* common/command.c */
 cmd_tbl_t *find_cmd(const char *cmd);
 
+#if defined(CONFIG_PEPPERCON)
+void command_enable_user(const char *cmd);
+#endif
+
 /*
  * Monitor Command
  *
@@ -85,13 +92,23 @@
 
 #ifdef  CFG_LONGHELP
 
-#define U_BOOT_CMD(name,maxargs,rep,cmd,usage,help) \
-cmd_tbl_t __u_boot_cmd_##name Struct_Section = {#name, maxargs, rep, cmd, usage, help}
+# ifdef CONFIG_PEPPERCON
+#  define U_BOOT_CMD(name,maxargs,rep,cmd,usage,help) \
+	cmd_tbl_t __u_boot_cmd_##name Struct_Section = {#name, maxargs, rep, cmd, usage, help, 0}
+# else /* !CONFIG_PEPPERCON */
+#  define U_BOOT_CMD(name,maxargs,rep,cmd,usage,help) \
+	cmd_tbl_t __u_boot_cmd_##name Struct_Section = {#name, maxargs, rep, cmd, usage, help}
+# endif /* !CONFIG_PEPPERCON */
 
 #else	/* no long help info */
 
-#define U_BOOT_CMD(name,maxargs,rep,cmd,usage,help) \
-cmd_tbl_t __u_boot_cmd_##name Struct_Section = {#name, maxargs, rep, cmd, usage}
+# ifdef CONFIG_PEPPERCON
+#  define U_BOOT_CMD(name,maxargs,rep,cmd,usage,help) \
+	cmd_tbl_t __u_boot_cmd_##name Struct_Section = {#name, maxargs, rep, cmd, usage, 0}
+# else /* !CONFIG_PEPPERCON */
+#  define U_BOOT_CMD(name,maxargs,rep,cmd,usage,help) \
+	cmd_tbl_t __u_boot_cmd_##name Struct_Section = {#name, maxargs, rep, cmd, usage}
+#endif /* !CONFIG_PEPPERCON */
 
 #endif	/* CFG_LONGHELP */
 
Index: include/common.h
===================================================================
RCS file: /srv/CVS/pplinux/u-boot/include/common.h,v
retrieving revision 1.1.333.1
retrieving revision 1.3
diff -u -r1.1.333.1 -r1.3
--- include/common.h	3 Feb 2005 09:43:16 -0000	1.1.333.1
+++ include/common.h	29 Apr 2005 08:43:30 -0000	1.3
@@ -147,7 +147,11 @@
 
 /* common/main.c */
 void	main_loop	(void);
+#ifdef CONFIG_PEPPERCON
+int	run_command	(const char *cmd, int flag, int);
+#else
 int	run_command	(const char *cmd, int flag);
+#endif
 int	readline	(const char *const prompt);
 void	init_cmd_timeout(void);
 void	reset_cmd_timeout(void);
@@ -155,13 +159,18 @@
 /* lib_$(ARCH)/board.c */
 void	board_init_f  (ulong);
 void	board_init_r  (gd_t *, ulong);
-int	checkboard    (void);
 int	checkflash    (void);
 int	checkdram     (void);
 char *	strmhz(char *buf, long hz);
 int	last_stage_init(void);
 extern ulong monitor_flash_len;
 
+#ifdef CONFIG_PEPPERCON
+unsigned char checkboard (void);
+#else
+int checkboard (void);
+#endif
+
 /* common/flash.c */
 void flash_perror (int);
 
@@ -278,6 +287,13 @@
 
 /* $(BOARD)/$(BOARD).c */
 int board_pre_init (void);
+#ifdef CONFIG_PEPPERCON
+int  board_serial_init (void);
+int  board_reinit_pll(void);
+# ifdef PP_FEAT_USBPOWERED
+void toggle_led_state(void);
+# endif
+#endif
 int board_post_init (void);
 int board_postclk_init (void); /* after clocks/timebase, before env/serial */
 void board_poweroff (void);
@@ -343,6 +359,9 @@
 void	serial_addr   (unsigned int);
 int	serial_getc   (void);
 int	serial_tstc   (void);
+#ifdef CONFIG_PEPPERCON
+int	serial_debug_cable_present (void);
+#endif
 
 /* $(CPU)/speed.c */
 int	get_clocks (void);
@@ -354,6 +373,7 @@
 #endif
 #ifdef CONFIG_4xx
 ulong	get_OPB_freq (void);
+ulong	get_EPB_freq (void);
 ulong	get_PCI_freq (void);
 #endif
 #if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
@@ -503,4 +523,13 @@
 void	show_boot_progress (int status);
 #endif
 
+#ifdef CONFIG_PEPPERCON
+
+/* defines for the default jumper/command setting */
+# define PP_DEFAULTS_NONE       0
+# define PP_DEFAULTS_JUMPER     1
+# define PP_DEFAULTS_COMMAND    2       
+
+#endif
+
 #endif	/* __COMMON_H_ */
Index: include/ppc405.h
===================================================================
RCS file: /srv/CVS/pplinux/u-boot/include/ppc405.h,v
retrieving revision 1.1.333.1
retrieving revision 1.3
diff -u -r1.1.333.1 -r1.3
--- include/ppc405.h	3 Feb 2005 09:43:16 -0000	1.1.333.1
+++ include/ppc405.h	6 Apr 2005 12:44:07 -0000	1.3
@@ -572,10 +572,14 @@
 #define malrxcarr  (MAL_DCR_BASE+0x11)  /* RX Channel active reg (Reset)     */
 #define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg   */
 #define malrxdeir  (MAL_DCR_BASE+0x13)  /* RX Descr. Error Int reg           */
-#define maltxctp0r (MAL_DCR_BASE+0x20)  /* TX 0 Channel table pointer reg    */
-#define maltxctp1r (MAL_DCR_BASE+0x21)  /* TX 1 Channel table pointer reg    */
-#define malrxctp0r (MAL_DCR_BASE+0x40)  /* RX 0 Channel table pointer reg    */
-#define malrcbs0   (MAL_DCR_BASE+0x60)  /* RX 0 Channel buffer size reg      */
+#define maltxctp0r_0 (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg    */
+#define maltxctp1r_0 (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg    */
+#define malrxctp0r_0 (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg    */
+#define malrcbs0_0   (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg      */
+#define maltxctp0r_1 (MAL_DCR_BASE+0x22) /* TX 0 Channel table pointer reg    */
+#define maltxctp1r_1 (MAL_DCR_BASE+0x23) /* TX 1 Channel table pointer reg    */
+#define malrxctp0r_1 (MAL_DCR_BASE+0x41) /* RX 0 Channel table pointer reg    */
+#define malrcbs0_1   (MAL_DCR_BASE+0x61) /* RX 0 Channel buffer size reg      */
 
 /*-----------------------------------------------------------------------------
 | IIC Register Offsets
Index: include/asm-ppc/global_data.h
===================================================================
RCS file: /srv/CVS/pplinux/u-boot/include/asm-ppc/global_data.h,v
retrieving revision 1.1.333.1
retrieving revision 1.2
diff -u -r1.1.333.1 -r1.2
--- include/asm-ppc/global_data.h	3 Feb 2005 09:43:16 -0000	1.1.333.1
+++ include/asm-ppc/global_data.h	3 Feb 2005 10:35:41 -0000	1.2
@@ -88,6 +88,13 @@
 #ifdef CONFIG_LWMON
 	unsigned long kbd_status;
 #endif
+#if defined(CONFIG_PEPPERCON)
+	unsigned int	debug_cable_present;
+	unsigned int	serial_debug;
+	unsigned int	devel_mode;
+	unsigned int	cable_kme;
+	unsigned char   hwid;
+#endif
 	void		**jt;		/* jump table */
 } gd_t;
 
Index: include/asm-ppc/u-boot.h
===================================================================
RCS file: /srv/CVS/pplinux/u-boot/include/asm-ppc/u-boot.h,v
retrieving revision 1.1.333.1
retrieving revision 1.3
diff -u -r1.1.333.1 -r1.3
--- include/asm-ppc/u-boot.h	3 Feb 2005 09:43:16 -0000	1.1.333.1
+++ include/asm-ppc/u-boot.h	29 Apr 2005 08:43:30 -0000	1.3
@@ -47,7 +47,8 @@
 #endif
 	unsigned long	bi_bootflags;	/* boot / reboot flag (for LynxOS) */
 	unsigned long	bi_ip_addr;	/* IP Address */
-	unsigned char	bi_enetaddr[6];	/* Ethernet adress */
+	unsigned char	bi_enetaddr[6]; /* Ethernet adress for 1st interface */
+	unsigned char	bi_enetaddr2[6]; /* Ethernet adress for 2nd interface */
 	unsigned short	bi_ethspeed;	/* Ethernet speed in Mbps */
 	unsigned long	bi_intfreq;	/* Internal Freq, in MHz */
 	unsigned long	bi_busfreq;	/* Bus Freq, in MHz */
@@ -95,6 +96,16 @@
 #if defined(CONFIG_NX823)
 	unsigned char	bi_sernum[8];
 #endif
+#ifdef CONFIG_PEPPERCON
+	unsigned int    bi_debug_mode;	/* 1 if debug cable was found on uart0*/
+	unsigned int	bi_def_jumper_set; /* defaults jumper/command state */
+	unsigned int	bi_cable_kme;   /* 1 if cable kme was found on uart0 */
+	unsigned int	bi_config_mode;	/* 1 if config cmd used for bootup */
+	unsigned int	bi_opb_busfreq;	/* OPB Bus speed, in Hz */
+	int		bi_iic_fast[1];	/* Use fast i2c mode */    
+	unsigned char   bi_hwid;	/* hardware id of the board */
+        unsigned int	bi_epb_busfreq;	/* EPB Bus speed, in Hz */
+#endif /* CONFIG_PEPPERCON */
 } bd_t;
 
 #endif /* __ASSEMBLY__ */
Index: include/configs/.dontdelete
===================================================================
RCS file: include/configs/.dontdelete
diff -N include/configs/.dontdelete
Index: include/configs/PEPPERCON.h
===================================================================
RCS file: include/configs/PEPPERCON.h
diff -N include/configs/PEPPERCON.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ include/configs/PEPPERCON.h	24 May 2005 14:01:50 -0000	1.5
@@ -0,0 +1,397 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Derived work: (C) Copyright 2002-2005 Peppercon AG
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Include our board specific stuff.
+ */
+#include <peppercon.h>
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#if PP_(CPU_TYPE, PP_HWID) == PP_CPU_405GP
+# define CONFIG_405GP		1
+#elif PP_(CPU_TYPE, PP_HWID) == PP_CPU_405EP
+# define CONFIG_405EP		1
+#else
+# error Unexpected processor type!
+#endif
+#define CONFIG_4xx		1	/* ...member of PPC4xx family */
+#define CONFIG_PEPPERCON	1	/* ...on a PEPPERCON board */
+#define CONFIG_BOARD_PRE_INIT	1	/* Call board_pre_init */
+#define CONFIG_BZIP2		1	/* We use bzip2 compressed images */
+#define DYNAMIC_CRC_TABLE	1	/* save some bytes */
+#define CONFIG_SYS_CLK_FREQ	PP_(SYS_CLK_FREQ, PP_HWID) /* external frequency to PLL */
+#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars */
+#define CONFIG_BOOTDELAY	3	/* autoboot delay */
+#define CONFIG_BAUDRATE		115200
+#if PP_(CONSOLE, PP_HWID) == PP_SERIAL_1
+# define CONFIG_UART1_CONSOLE 1
+#endif
+
+
+/*
+ * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
+ * The Linux BASE_BAUD define should match this configuration.
+ *    baseBaud = cpuClock/(uartDivisor*16)
+ * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#undef  CFG_EXT_SERIAL_CLOCK	/* external serial clock */
+#undef  CFG_405_UART_ERRATA_59	/* 405GP/CR Rev. D silicon */
+#define CFG_BASE_BAUD		691200
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+/*
+ * Size (bytes) of interrupt driven serial port buffer.
+ * Set to 0 to use polling instead of interrupts.
+ * Setting to 0 will also disable RTS/CTS handshaking.
+ */
+#if 0
+# define CONFIG_SERIAL_SOFTWARE_FIFO 4000
+#else
+# undef  CONFIG_SERIAL_SOFTWARE_FIFO
+#endif
+
+
+/*
+ * if PP_PRODUCTION, we use environment options (also depending on hardware)
+ * to autoboot directly from the production NFS server to start
+ * flashing the firmware or to switch the OEM version
+ * if !PP_PRODUCTION, the default (ramdisk...) env options are used
+ */
+
+#ifdef PP_PRODUCTION
+
+/* PP_PRODUCTION */
+
+#  undef CFG_SERIAL_DEBUG       /* don't test for serial debug cable */
+#  define CONFIG_BOOTCOMMAND	"tftpboot"
+#  define CONFIG_ETHADDR	FE:00:00:FF:00:00
+#  define CONFIG_SERVERIP	192.168.5.1
+#  define CFG_AUTOLOAD  	"yes"
+#  define CONFIG_EXTRA_ENV_SETTINGS       \
+    "autostart=yes\0"			  \
+    "serial_debug=1\0"
+
+#  define CONFIG_IPADDR	192.168.5.22
+#  define CONFIG_BOOTFILE zImage.lara.kim.prod
+#  define ROOTFS_PRODUCTION /install_root_devel
+
+#  define CONFIG_BOOTARGS						\
+    _CONFIG_BOOTARGS_PRODUCTION(CONFIG_IPADDR, ROOTFS_PRODUCTION)
+
+#  define _CONFIG_BOOTARGS_PRODUCTION(ip, rootfs)	\
+    __CONFIG_BOOTARGS_PRODUCTION(ip, rootfs)
+
+#  define __CONFIG_BOOTARGS_PRODUCTION(ip, rootfs)	\
+    "console=ttyS0,115200 root=/dev/nfs "		\
+    "nfsroot=192.168.5.1:" #rootfs			\
+    " ip=" #ip ":192.168.5.1 "				\
+    "wdt=90 rw " PP_BIGPHYSAREA_OPT(PP_HWID)
+
+#else
+
+/* NOT PP_PRODUCTION */
+
+#  define CFG_SERIAL_DEBUG	1	/* test for serial debug cable */
+#  if PP_(FLASH_SIZE,PP_HWID) == (4*1024*1024)
+#    define CONFIG_BOOTCOMMAND	"bootm ffc00000 ffcc0000"
+#  elif PP_(FLASH_SIZE,PP_HWID) == (8*1024*1024)
+#    define CONFIG_BOOTCOMMAND	"bootm ff800000 ff8e0000"
+#  elif PP_(FLASH_SIZE,PP_HWID) == (16*1024*1024)
+#    define CONFIG_BOOTCOMMAND	"bootm ff000000 ff0e0000"
+#  else
+#    error Unexpected flash size!
+#  endif
+
+
+#  ifdef CONFIG_UART1_CONSOLE
+#    define CONFIG_BOOTARGS    "console=ttyS1,115200 root=/dev/ram " \
+                               "ramdisk_size=8192 init=/sbin/init "  \
+                               "ip=off wdt=90 rw " PP_BIGPHYSAREA_OPT(PP_HWID)
+#  else
+#    define CONFIG_BOOTARGS    "console=ttyS0,115200 root=/dev/ram " \
+                               "ramdisk_size=8192 init=/sbin/init "  \
+                               "ip=off wdt=90 rw " PP_BIGPHYSAREA_OPT(PP_HWID)
+#  endif
+#endif
+
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+#define CONFIG_MII		1	/* MII PHY management */
+#define	CONFIG_PREF_PHY_ADDR	1	/* Prefered PHY address (for >1 PHY) */
+
+#define CONFIG_COMMANDS		(CFG_CMD_BDI		\
+				 | CFG_CMD_BOOTD	\
+				 | CFG_CMD_IMI		\
+				 | CFG_CMD_FLASH	\
+				 | CFG_CMD_MEMORY	\
+				 | CFG_CMD_NET		\
+				 | CFG_CMD_ENV		\
+				 | CFG_CMD_PCI		\
+				 | CFG_CMD_RUN		\
+				 | CFG_CMD_LOADB	\
+				 )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#undef CFG_LONGHELP			/* undef to save memory */
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+# define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on */
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM */
+#define CFG_LOAD_ADDR		0x200000	/* default load address */
+#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
+#undef  CONFIG_SOFT_I2C			/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER	0	/* configure as pci adapter     */
+#define PCI_HOST_FORCE		1	/* configure as pci host        */
+#define PCI_HOST_AUTO		2       /* detected via arbiter enable  */
+
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_HOST	PCI_HOST_FORCE  /* select pci host function     */
+#undef CONFIG_PCI_PNP			/* no pci plug-and-play         */
+					/* resource configuration       */
+
+#define CFG_PCI_VENDORID 0x1743		/* PCI Vendor ID: Peppercon AG  */
+#define CFG_PCI_DEVICEID 0x0405		/* PCI Device ID: 405           */
+#define CFG_PCI_SUBSYS_VENDORID 0x1743	/* PCI Vendor ID: Peppercon AG  */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: 405           */
+
+#define CFG_PCI_CLASSCODE 0x0600	/* PCI Class Code: Bridge	*/
+
+/* --- PCI resources ---- */
+
+/* PLB -> PCI Region 0 */
+#define CFG_PCI_PMM0LA    0x80000000    /* map PCI MEM			*/
+#define CFG_PCI_PMM0PCILA 0x80000000
+#define CFG_PCI_PMM0PCIHA 0x00000000
+#define CFG_PCI_PMM0MA    0xC0000001    /* 1GB; no prefetching; enable	*/
+
+/* PLB -> PCI Region 1 */
+#define CFG_PCI_PMM1LA    0x00000000	/* disabled			*/
+#define CFG_PCI_PMM1PCILA 0x00000000
+#define CFG_PCI_PMM1PCIHA 0x00000000
+#define CFG_PCI_PMM1MA    0x00000000
+
+/* PLB -> PCI Region 2 */
+#define CFG_PCI_PMM2LA     0x00000000	/* disabled			*/
+#define CFG_PCI_PMM2PCILA  0x00000000
+#define CFG_PCI_PMM2PCIHA  0x00000000
+#define CFG_PCI_PMM2MA     0x00000000
+
+/* PCI -> PLB Region 1 */
+#define CFG_PCI_PTM1LA     0x00000000	/* point to PPC memory          */
+#define CFG_PCI_PTM1MS	   0xFC000001	/* 64 MB			*/
+#define CFG_PCI_PTM1PCI    0x00000000   /* Host: use this pci address   */
+	
+/* PCI -> PLB Region 2 */
+#define CFG_PCI_PTM2LA     0x00000000   /* disabled			*/
+#define CFG_PCI_PTM2MS     0x00000000
+#define CFG_PCI_PTM2PCI    0x00000000
+
+/* --------------------------------------------------------------------------
+ * GPIO stuff (only for PPC405EP)
+ */
+#ifdef CONFIG_405EP
+# define CFG_GPIO0_OSRH  PP_CALC_GPIO0_OSRH(PP_HWID)
+# define CFG_GPIO0_OSRL  PP_CALC_GPIO0_OSRL(PP_HWID)
+# define CFG_GPIO0_ISR1H 0x55555555
+# define CFG_GPIO0_ISR1L 0x55555555
+# define CFG_GPIO0_TSRH  0x00000000
+# define CFG_GPIO0_TSRL  0x00000000
+# define CFG_GPIO0_TCR   PP_CALC_GPIO0_TCR(PP_HWID)
+#endif
+
+/* --------------------------------------------------------------------------
+ * External Bus Controller
+ */
+
+/* The Peripheral Bank Access Parameters */
+#define CFG_EBC_PB0AP	PP_CALC_EBC0_BnAP(PP_HWID, 00)
+#define CFG_EBC_PB1AP	PP_CALC_EBC0_BnAP(PP_HWID, 01)
+#define CFG_EBC_PB2AP	PP_CALC_EBC0_BnAP(PP_HWID, 02)
+#define CFG_EBC_PB3AP	PP_CALC_EBC0_BnAP(PP_HWID, 03)
+#define CFG_EBC_PB4AP	PP_CALC_EBC0_BnAP(PP_HWID, 04)
+#ifndef CONFIG_405EP /* PPC405EP has only 5 chip selects */
+# define CFG_EBC_PB5AP	PP_CALC_EBC0_BnAP(PP_HWID, 05)
+# define CFG_EBC_PB6AP	PP_CALC_EBC0_BnAP(PP_HWID, 06)
+# define CFG_EBC_PB7AP	PP_CALC_EBC0_BnAP(PP_HWID, 07)
+#endif
+
+/* The Peripheral Bank Configuration Registers */
+#define CFG_EBC_PB0CR	PP_CALC_EBC0_BnCR(PP_HWID, 00)
+#define CFG_EBC_PB1CR	PP_CALC_EBC0_BnCR(PP_HWID, 01)
+#define CFG_EBC_PB2CR	PP_CALC_EBC0_BnCR(PP_HWID, 02)
+#define CFG_EBC_PB3CR	PP_CALC_EBC0_BnCR(PP_HWID, 03)
+#define CFG_EBC_PB4CR	PP_CALC_EBC0_BnCR(PP_HWID, 04)
+#ifndef CONFIG_405EP /* PPC405EP has only 5 chip selects */
+# define CFG_EBC_PB5CR	PP_CALC_EBC0_BnCR(PP_HWID, 05)
+# define CFG_EBC_PB6CR	PP_CALC_EBC0_BnCR(PP_HWID, 06)
+# define CFG_EBC_PB7CR	PP_CALC_EBC0_BnCR(PP_HWID, 07)
+#endif
+
+/* The EBC Configuration Register */
+#define CFG_EBC_EPCR	PP_CALC_EBC0_CFG(PP_HWID)
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		(0x0 - PP_(FLASH_SIZE, PP_HWID))
+#define CFG_MONITOR_BASE	0xFFFE0000	/* last 128 kB */
+#define CFG_MONITOR_LEN		(128 * 1024)	/* Reserve 128 kB for Monitor */
+#define CFG_MALLOC_LEN		(8192 * 1024)	/* Reserve 8MB for malloc() */
+						/* ... because of bzip2 */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Mem-map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */
+#define CFG_FLASH_INCREMENT	0	/* there is only one bank */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CFG_SECT_SIZE		(128*1024) /* sector size in bytes */
+#define CFG_MAX_FLASH_SECT	(PP_(FLASH_SIZE, PP_HWID) / CFG_SECT_SIZE) /* max number of sectors on one chip */
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+
+/*
+ * NOTE: The environment is placed via the linker script 'u-boot.lds' at the
+ *       end of the boot monitor right before the reset vector.
+ */
+#ifdef CFG_ENV_IS_IN_FLASH
+# define CFG_ENV_SECT_SIZE	(128*1024) /* environment sector total size */
+# define CFG_ENV_SIZE		512	/* environment size */
+# define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN - CFG_ENV_SIZE - 0x10) /* let space for reset vector */
+# define CFG_ENV_OFFSET		(CFG_ENV_ADDR - CFG_FLASH_BASE)
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#ifdef CONFIG_405EP
+# define CFG_DCACHE_SIZE	16384
+#else
+# define CFG_DCACHE_SIZE	 8192
+#endif
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+#undef CFG_INIT_DCACHE_CS	/* no stack in data cache memory */
+#define CFG_INIT_RAM_ADDR	0x00df0000 /* Inside of SDRAM */
+#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM */
+#define CFG_GBL_DATA_SIZE	140	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+# define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+#ifdef CONFIG_405EP
+# define PLLMR0_DEFAULT PP_PLLMR0_DEFAULT(PP_HWID)
+# define PLLMR1_DEFAULT PP_PLLMR1_DEFAULT(PP_HWID)
+# define DYNAMIC_PLL	PP_DYNAMIC_PLL(PP_HWID)
+# if (PP_DYNAMIC_PLL(PP_HWID) == 1)
+#  define PLLMR0_SLOW	PP_PLLMR0_SLOW(PP_HWID)
+#  define PLLMR1_SLOW	PP_PLLMR1_SLOW(PP_HWID)
+#  define PLLMR0_FAST	PP_PLLMR0_FAST(PP_HWID)
+#  define PLLMR1_FAST	PP_PLLMR1_FAST(PP_HWID)
+#  define CPU_CLK_SLOW	PP_CPU_CLK_SLOW(PP_HWID)
+#  define CPU_CLK_FAST	PP_CPU_CLK_FAST(PP_HWID)
+# endif
+#endif
+
+#endif	/* __CONFIG_H */
Index: lib_generic/bzlib_decompress.c
===================================================================
RCS file: /srv/CVS/pplinux/u-boot/lib_generic/bzlib_decompress.c,v
retrieving revision 1.1.333.1
retrieving revision 1.2
diff -u -r1.1.333.1 -r1.2
--- lib_generic/bzlib_decompress.c	3 Feb 2005 09:43:19 -0000	1.1.333.1
+++ lib_generic/bzlib_decompress.c	3 Feb 2005 10:35:41 -0000	1.2
@@ -1,4 +1,5 @@
 #include <config.h>
+#include <common.h>
 #ifdef CONFIG_BZIP2
 
 /*-------------------------------------------------------------*/
@@ -151,7 +152,10 @@
    Int32      retVal;
    Int32      minLen, maxLen;
    bz_stream* strm = s->strm;
-
+#if defined(CONFIG_PEPPERCON) && defined(PP_FEAT_USBPOWERED)
+   unsigned int led_count = 0;
+#endif
+   
    /* stuff that needs to be saved/restored */
    Int32  i;
    Int32  j;
@@ -415,14 +419,19 @@
       GET_MTF_VAL(BZ_X_MTF_1, BZ_X_MTF_2, nextSym);
 
       while (True) {
-
+#if defined(CONFIG_PEPPERCON) && defined(PP_FEAT_USBPOWERED)
+	  if ((led_count++ % 10000) == 0) {
+	      toggle_led_state();
+	  }
+#endif
+	  
 	 if (nextSym == EOB) break;
 
 	 if (nextSym == BZ_RUNA || nextSym == BZ_RUNB) {
 
 	    es = -1;
 	    N = 1;
-	    do {
+	    do {		
 	       if (nextSym == BZ_RUNA) es = es + (0+1) * N; else
 	       if (nextSym == BZ_RUNB) es = es + (1+1) * N;
 	       N = N * 2;
@@ -531,7 +540,7 @@
       BZ_INITIALISE_CRC ( s->calculatedBlockCRC );
       s->state = BZ_X_OUTPUT;
       if (s->verbosity >= 2) VPrintf0 ( "rt+rld" );
-
+      
       /*-- Set up cftab to facilitate generation of T^(-1) --*/
       s->cftab[0] = 0;
       for (i = 1; i <= 256; i++) s->cftab[i] = s->unzftab[i-1];
@@ -588,7 +597,6 @@
 	 } else {
 	    BZ_GET_FAST(s->k0); s->nblock_used++;
 	 }
-
       }
 
       RETURN(BZ_OK);
Index: lib_generic/crc32.c
===================================================================
RCS file: /srv/CVS/pplinux/u-boot/lib_generic/crc32.c,v
retrieving revision 1.1.333.1
retrieving revision 1.2
diff -u -r1.1.333.1 -r1.2
--- lib_generic/crc32.c	3 Feb 2005 09:43:19 -0000	1.1.333.1
+++ lib_generic/crc32.c	3 Feb 2005 10:35:41 -0000	1.2
@@ -20,9 +20,7 @@
 
 #ifdef DYNAMIC_CRC_TABLE
 
-local int crc_table_empty = 1;
-local uLongf crc_table[256];
-local void make_crc_table OF((void));
+local void make_crc_table OF((uLongf * crc_table));
 
 /*
   Generate a table for a byte-wise 32-bit CRC calculation on the polynomial:
@@ -48,7 +46,7 @@
   the information needed to generate CRC's on data a byte at a time for all
   combinations of CRC register values and incoming bytes.
 */
-local void make_crc_table()
+local void make_crc_table(uLongf * crc_table)
 {
   uLong c;
   int n, k;
@@ -68,7 +66,6 @@
       c = c & 1 ? poly ^ (c >> 1) : c >> 1;
     crc_table[n] = c;
   }
-  crc_table_empty = 0;
 }
 #else
 /* ========================================================================
@@ -156,8 +153,8 @@
     uInt len;
 {
 #ifdef DYNAMIC_CRC_TABLE
-    if (crc_table_empty)
-      make_crc_table();
+    uLongf crc_table[256];
+    make_crc_table(crc_table);
 #endif
     crc = crc ^ 0xffffffffL;
     while (len >= 8)
@@ -179,8 +176,8 @@
 uLong ZEXPORT crc32_no_comp(uLong crc, const Bytef *buf, uInt len)
 {
 #ifdef DYNAMIC_CRC_TABLE
-    if (crc_table_empty)
-      make_crc_table();
+    uLongf crc_table[256];
+    make_crc_table(crc_table);
 #endif
     while (len >= 8)
     {
Index: lib_ppc/board.c
===================================================================
RCS file: /srv/CVS/pplinux/u-boot/lib_ppc/board.c,v
retrieving revision 1.1.333.1
retrieving revision 1.3
diff -u -r1.1.333.1 -r1.3
--- lib_ppc/board.c	3 Feb 2005 09:43:34 -0000	1.1.333.1
+++ lib_ppc/board.c	29 Apr 2005 08:43:30 -0000	1.3
@@ -270,7 +270,11 @@
 #endif
 	env_init,
 	init_baudrate,
+#ifdef CONFIG_PEPPERCON
+	board_serial_init,
+#else /* !CONFIG_PEPPERCON */
 	serial_init,
+#endif /* !CONFIG_PEPPERCON */
 	console_init_f,
 	display_options,
 #if defined(CONFIG_8260)
@@ -281,7 +285,9 @@
 #if defined(CONFIG_MPC5XXX)
 	prt_mpc5xxx_clks,
 #endif /* CONFIG_MPC5XXX */
+#ifndef CONFIG_PEPPERCON
 	checkboard,
+#endif
 	INIT_FUNC_WATCHDOG_INIT
 #if defined(CONFIG_BMW)		|| \
     defined(CONFIG_COGENT)	|| \
@@ -294,6 +300,9 @@
 #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
 	init_func_i2c,
 #endif
+#if defined(CONFIG_PEPPERCON) && (DYNAMIC_PLL == 1)
+	board_reinit_pll,
+#endif
 #if defined(CONFIG_DTT)		/* Digital Thermometers and Thermostats */
 	dtt_init,
 #endif
@@ -340,6 +349,10 @@
 	uchar tmp[64];		/* long enough for environment variables */
 #endif
 
+#ifdef CONFIG_PEPPERCON
+	int defaults_jumper_set;
+#endif /* CONFIG_PEPPERCON */
+
 	/* Pointer is writable since we allocated a register for it */
 	gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
 
@@ -348,6 +361,20 @@
 	memset ((void *) gd, 0, sizeof (gd_t));
 #endif
 
+#ifdef CONFIG_PEPPERCON
+	/*
+	 * determine defaults jumper state - this must be before board_pre_init()
+	 *
+	 * NOTE: On eRIC 1.x (hardware id 0) this jumper is low active.
+	 */
+# if (PP_HWID_INT == 0x00)
+	defaults_jumper_set = (in32(GPIO0_IR) & 0x08000000) ? 0 : PP_DEFAULTS_JUMPER;
+# else
+	defaults_jumper_set = (in32(GPIO0_IR) & 0x04000000) ? PP_DEFAULTS_JUMPER : 0;
+# endif
+
+#endif /* CONFIG_PEPPERCON */
+
 	for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
 		if ((*init_fnc_ptr) () != 0) {
 			hang ();
@@ -504,6 +531,17 @@
 #endif
 #endif
 
+#ifdef CONFIG_PEPPERCON
+	bd->bi_debug_mode = gd->serial_debug;
+	bd->bi_def_jumper_set = defaults_jumper_set;
+	bd->bi_cable_kme = gd->cable_kme;
+	bd->bi_config_mode = 0; /* per default don't start the config tool */
+	bd->bi_opb_busfreq = get_OPB_freq();
+	bd->bi_epb_busfreq = get_EPB_freq();
+	bd->bi_iic_fast[0] = 0;
+	bd->bi_hwid = gd->hwid;
+#endif
+
 	debug ("New Stack Pointer is: %08lx\n", addr_sp);
 
 	WATCHDOG_RESET ();
@@ -518,7 +556,7 @@
 	memcpy (id, (void *)gd, sizeof (gd_t));
 
 	relocate_code (addr_sp, id, addr);
-
+       
 	/* NOTREACHED - relocate_code() does not return */
 }
 
@@ -555,7 +593,7 @@
 	gd->flags |= GD_FLG_RELOC;	/* tell others: relocation done */
 
 	debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
-
+	
 	WATCHDOG_RESET ();
 
 	gd->reloc_off = dest_addr - CFG_MONITOR_BASE;
@@ -609,6 +647,7 @@
 #if defined(CONFIG_IP860) || defined(CONFIG_PCU_E) || defined (CONFIG_FLAGADM)
 	icache_enable ();	/* it's time to enable the instruction cache */
 #endif
+	//dcache_enable ();
 
 #if defined(CFG_INIT_RAM_LOCK) && defined(CONFIG_E500)
        unlock_ram_in_cache();  /* it's time to unlock D-cache in e500 */
@@ -680,6 +719,10 @@
 	bd->bi_flashoffset = 0;
 #endif /* !CFG_NO_FLASH */
 
+#ifdef CONFIG_PEPPERCON
+	bd->bi_hwid = checkboard();
+#endif
+	
 	WATCHDOG_RESET ();
 
 	/* initialize higher level parts of CPU like time base and timers */
@@ -955,6 +998,14 @@
  }
 #endif
 
+#ifdef CONFIG_PEPPERCON
+	command_enable_user("erla");
+	command_enable_user("reset");
+	command_enable_user("config");
+	command_enable_user("defaults");
+	command_enable_user("help");
+#endif
+
 	/* Initialization complete - start the monitor */
 
 	/* main_loop() can return to retry autoboot, if so just run it again. */
Index: net/net.c
===================================================================
RCS file: /srv/CVS/pplinux/u-boot/net/net.c,v
retrieving revision 1.1.333.1
retrieving revision 1.2
diff -u -r1.1.333.1 -r1.2
--- net/net.c	3 Feb 2005 09:43:35 -0000	1.1.333.1
+++ net/net.c	3 Feb 2005 10:35:41 -0000	1.2
@@ -61,6 +61,7 @@
 #include <common.h>
 #include <watchdog.h>
 #include <command.h>
+#include <malloc.h>
 #include <net.h>
 #include "bootp.h"
 #include "tftp.h"
@@ -126,7 +127,7 @@
 static void PingStart(void);
 #endif
 
-volatile uchar	PktBuf[(PKTBUFSRX+1) * PKTSIZE_ALIGN + PKTALIGN];
+volatile uchar	* PktBuf = NULL;
 
 volatile uchar *NetRxPackets[PKTBUFSRX]; /* Receive packets			*/
 
@@ -241,10 +242,15 @@
 	if (!NetTxPacket) {
 		int	i;
 
+		if (!PktBuf) {
+		    PktBuf = malloc((PKTBUFSRX+1) * PKTSIZE_ALIGN + PKTALIGN);
+		    if (!PktBuf) return(-1);
+		}
+
 		/*
 		 *	Setup packet buffers, aligned correctly.
 		 */
-		NetTxPacket = &PktBuf[0] + (PKTALIGN - 1);
+		NetTxPacket = PktBuf + (PKTALIGN - 1);
 		NetTxPacket -= (ulong)NetTxPacket % PKTALIGN;
 		for (i = 0; i < PKTBUFSRX; i++) {
 			NetRxPackets[i] = NetTxPacket + (i+1)*PKTSIZE_ALIGN;
@@ -300,6 +306,7 @@
 		}
 
 		break;
+#if defined(CONFIG_RARP) || defined(CONFIG_RARP)
 	case BOOTP:
 	case RARP:
 		/*
@@ -309,6 +316,7 @@
 		NetOurIP = 0;
 		NetServerIP = 0;
 		break;
+#endif
 	default:
 		break;
 	}
@@ -343,15 +351,20 @@
 			break;
 #endif /* CFG_CMD_DHCP */
 
+#ifdef CONFIG_BOOTP
 		case BOOTP:
 			BootpTry = 0;
 			BootpRequest ();
 			break;
+#endif
 
+#ifdef CONFIG_RARP
 		case RARP:
 			RarpTry = 0;
 			RarpRequest ();
 			break;
+#endif
+
 #if (CONFIG_COMMANDS & CFG_CMD_PING)
 		case PING:
 			PingStart();
@@ -793,6 +806,7 @@
 			return;
 		}
 
+#ifdef CONFIG_RARP
 	case PROT_RARP:
 #ifdef ET_DEBUG
 		printf("Got RARP\n");
@@ -817,7 +831,7 @@
 			(*packetHandler)(0,0,0,0);
 		}
 		break;
-
+#endif
 	case PROT_IP:
 #ifdef ET_DEBUG
 		printf("Got IP\n");
@@ -935,6 +949,7 @@
 			}
 			/* Fall through */
 
+#if (CONFIG_COMMANDS & CFG_CMD_PING) || defined(CONFIG_BOOTP) || defined(CONFIG_RARP)
 	case DHCP:
 	case RARP:
 	case BOOTP:
@@ -963,6 +978,7 @@
 			    return (1);
 #endif
 			}
+#endif
 			/* Fall through */
 		default:
 			return(0);
Index: tools/Makefile
===================================================================
RCS file: /srv/CVS/pplinux/u-boot/tools/Makefile,v
retrieving revision 1.1.333.1
retrieving revision 1.2
diff -u -r1.1.333.1 -r1.2
--- tools/Makefile	3 Feb 2005 09:43:18 -0000	1.1.333.1
+++ tools/Makefile	3 Feb 2005 10:35:41 -0000	1.2
@@ -111,7 +111,7 @@
 #
 # Use native tools and options
 #
-CPPFLAGS   = -I../include -I.. -DTEXT_BASE=$(TEXT_BASE) -DUSE_HOSTCC
+CPPFLAGS   = -I../include -I.. -I$(TOPDIR)/board/$(BOARD) -DTEXT_BASE=$(TEXT_BASE) -DUSE_HOSTCC $(FW_CPPFLAGS)
 CFLAGS     = $(HOST_CFLAGS) $(CPPFLAGS) -O
 AFLAGS	   = -D__ASSEMBLY__ $(CPPFLAGS)
 CC	   = $(HOSTCC)
